| Line 57... |
Line 57... |
# 25 MHz Ethernet MII receive clock
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# 25 MHz Ethernet MII receive clock
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NET "mrx_clk_pad_i" TNM_NET = "MRX_CLK";
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NET "mrx_clk_pad_i" TNM_NET = "MRX_CLK";
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TIMESPEC "TS_MRX_CLK" = PERIOD "MRX_CLK" 40.0 ns HIGH 50 %;
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TIMESPEC "TS_MRX_CLK" = PERIOD "MRX_CLK" 40.0 ns HIGH 50 %;
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# False paths between clocks
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# False paths between clocks
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PIN "u_mcb_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK";
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PIN "u_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK";
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PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "SYS_CLK";
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PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "CLKOUT2";
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TIMESPEC "TS_false2" = FROM "DDR_CLK" TO "CLKOUT2" TIG;
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############################################################################
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# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
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# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
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# follows the corresponding GUI option setting. However, DDR3 can operate at higher
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# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
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# remove/edit the below constraint to avoid false errors.
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############################################################################
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CONFIG MCB_PERFORMANCE= EXTENDED;
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##################################################################################
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# Timing Ignore constraints for paths crossing the clock domain
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##################################################################################
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NET "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
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NET "u_ddr3/c?_pll_lock" TIG;
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INST "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
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TIMESPEC "TS_false1" = FROM "DDR_CLK" TO "SYS_CLK" TIG;
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############################################################################
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############################################################################
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## I/O TERMINATION
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## I/O TERMINATION
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############################################################################
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############################################################################
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| Line 89... |
Line 107... |
NET "ddr3_we_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_we_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_odt" IOSTANDARD = SSTL15_II;
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NET "ddr3_odt" IOSTANDARD = SSTL15_II;
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NET "ddr3_reset_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_reset_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_dm[*]" IOSTANDARD = SSTL15_II;
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NET "ddr3_dm[*]" IOSTANDARD = SSTL15_II;
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NET "mcb3_rzq" IOSTANDARD = SSTL15_II;
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NET "mcb3_rzq" IOSTANDARD = SSTL15_II;
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NET "mcb3_zio" IOSTANDARD = SSTL15_II;
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#NET "mcb3_zio" IOSTANDARD = SSTL15_II;
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NET "brd_clk_p" IOSTANDARD = LVDS_25;
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NET "brd_clk_p" IOSTANDARD = LVDS_25;
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NET "brd_clk_n" IOSTANDARD = LVDS_25;
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NET "brd_clk_n" IOSTANDARD = LVDS_25;
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NET "brd_rst" IOSTANDARD = LVCMOS15;
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NET "brd_rst" IOSTANDARD = LVCMOS15;
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NET "mtx_clk_pad_i" IOSTANDARD = LVCMOS25;
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NET "mtx_clk_pad_i" IOSTANDARD = LVCMOS25;
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| Line 179... |
Line 197... |
NET "ddr3_dqs_n[1]" LOC = "V1" ;
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NET "ddr3_dqs_n[1]" LOC = "V1" ;
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NET "ddr3_we_n" LOC = "H2" ;
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NET "ddr3_we_n" LOC = "H2" ;
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# The following pins are available for used as RZQ or ZIO pins#
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# The following pins are available for used as RZQ or ZIO pins#
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NET "mcb3_rzq" LOC = "K7" ;
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NET "mcb3_rzq" LOC = "K7" ;
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NET "mcb3_zio" LOC = "R7" ;
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#NET "mcb3_zio" LOC = "R7" ;
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############################################################################
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############################################################################
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# Ethernet MII MAC to PHY interface
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# Ethernet MII MAC to PHY interface
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############################################################################
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############################################################################
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NET "mtx_clk_pad_i" LOC = "L20" ;
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NET "mtx_clk_pad_i" LOC = "L20" ;
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