//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// RAM-based register Bank for Amber Core //
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// RAM-based register Bank for Amber Core //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Contains 37 32-bit registers, 16 of which are visible //
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// Contains 37 32-bit registers, 16 of which are visible //
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// ina any one operating mode. //
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// ina any one operating mode. //
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// The block is designed using syncronous RAM primitive, //
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// The block is designed using syncronous RAM primitive, //
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// and fits well into an FPGA design //
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// and fits well into an FPGA design //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no //
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// - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module a23_ram_register_bank (
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module a23_ram_register_bank (
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input i_clk,
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input i_clk,
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input i_fetch_stall,
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input i_fetch_stall,
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input [1:0] i_mode_exec, // registered cpu mode from execution stage
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input [1:0] i_mode_exec, // registered cpu mode from execution stage
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input [1:0] i_mode_exec_nxt, // 1 periods delayed from i_mode_idec
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input [1:0] i_mode_exec_nxt, // 1 periods delayed from i_mode_idec
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// Used for register reads
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// Used for register reads
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input [1:0] i_mode_rds_exec, // Use raw version in this implementation,
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input [1:0] i_mode_rds_exec, // Use raw version in this implementation,
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// includes i_user_mode_regs_store
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// includes i_user_mode_regs_store
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input i_user_mode_regs_load,
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input i_user_mode_regs_load,
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input [3:0] i_rm_sel,
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input [3:0] i_rm_sel,
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input [3:0] i_rds_sel,
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input [3:0] i_rds_sel,
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input [3:0] i_rn_sel,
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input [3:0] i_rn_sel,
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input i_pc_wen,
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input i_pc_wen,
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input [3:0] i_reg_bank_wsel,
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input [3:0] i_reg_bank_wsel,
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input [23:0] i_pc, // program counter [25:2]
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input [23:0] i_pc, // program counter [25:2]
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input [31:0] i_reg,
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input [31:0] i_reg,
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input [3:0] i_status_bits_flags,
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input [3:0] i_status_bits_flags,
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input i_status_bits_irq_mask,
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input i_status_bits_irq_mask,
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input i_status_bits_firq_mask,
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input i_status_bits_firq_mask,
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output [31:0] o_rm,
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output [31:0] o_rm,
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output [31:0] o_rs,
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output [31:0] o_rs,
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output [31:0] o_rd,
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output [31:0] o_rd,
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output [31:0] o_rn,
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output [31:0] o_rn,
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output [31:0] o_pc
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output [31:0] o_pc
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);
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);
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`include "a23_localparams.v"
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`include "a23_localparams.vh"
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`include "a23_functions.v"
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`include "a23_functions.vh"
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wire [1:0] mode_idec;
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wire [1:0] mode_idec;
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wire [1:0] mode_exec;
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wire [1:0] mode_exec;
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wire [1:0] mode_rds;
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wire [1:0] mode_rds;
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wire [4:0] rm_addr;
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wire [4:0] rm_addr;
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wire [4:0] rds_addr;
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wire [4:0] rds_addr;
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wire [4:0] rn_addr;
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wire [4:0] rn_addr;
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wire [4:0] wr_addr;
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wire [4:0] wr_addr;
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// Register pool in embedded ram memory
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// Register pool in embedded ram memory
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reg [31:0] reg_ram_n[31:0];
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reg [31:0] reg_ram_n[31:0];
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reg [31:0] reg_ram_m[31:0];
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reg [31:0] reg_ram_m[31:0];
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reg [31:0] reg_ram_ds[31:0];
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reg [31:0] reg_ram_ds[31:0];
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wire [31:0] rds_out;
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wire [31:0] rds_out;
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wire [31:0] rm_out;
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wire [31:0] rm_out;
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wire [31:0] rn_out;
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wire [31:0] rn_out;
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// Synchronous ram input buffering
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// Synchronous ram input buffering
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reg [4:0] rm_addr_reg;
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reg [4:0] rm_addr_reg;
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reg [4:0] rds_addr_reg;
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reg [4:0] rds_addr_reg;
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reg [4:0] rn_addr_reg;
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reg [4:0] rn_addr_reg;
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// User Mode Registers
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// User Mode Registers
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reg [23:0] r15 = 24'hc0_ffee;
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reg [23:0] r15 = 24'hc0_ffee;
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wire [31:0] r15_out_rm;
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wire [31:0] r15_out_rm;
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wire [31:0] r15_out_rm_nxt;
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wire [31:0] r15_out_rm_nxt;
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wire [31:0] r15_out_rn;
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wire [31:0] r15_out_rn;
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// r15 selectors
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// r15 selectors
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reg rn_15 = 1'b0;
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reg rn_15 = 1'b0;
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reg rm_15 = 1'b0;
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reg rm_15 = 1'b0;
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reg rds_15 = 1'b0;
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reg rds_15 = 1'b0;
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// Write Enables from execute stage
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// Write Enables from execute stage
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assign mode_idec = i_mode_exec_nxt & ~{2{i_user_mode_regs_load}};
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assign mode_idec = i_mode_exec_nxt & ~{2{i_user_mode_regs_load}};
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assign wr_addr = reg_addr(mode_idec, i_reg_bank_wsel);
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assign wr_addr = reg_addr(mode_idec, i_reg_bank_wsel);
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// Read Enables from stage 1 (fetch)
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// Read Enables from stage 1 (fetch)
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assign mode_exec = i_mode_exec_nxt;
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assign mode_exec = i_mode_exec_nxt;
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assign rm_addr = reg_addr(mode_exec, i_rm_sel);
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assign rm_addr = reg_addr(mode_exec, i_rm_sel);
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assign rn_addr = reg_addr(mode_exec, i_rn_sel);
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assign rn_addr = reg_addr(mode_exec, i_rn_sel);
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// Rds
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// Rds
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assign mode_rds = i_mode_rds_exec;
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assign mode_rds = i_mode_rds_exec;
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assign rds_addr = reg_addr(mode_rds, i_rds_sel);
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assign rds_addr = reg_addr(mode_rds, i_rds_sel);
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// ========================================================
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// ========================================================
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// r15 Register Read based on Mode
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// r15 Register Read based on Mode
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// ========================================================
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// ========================================================
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assign r15_out_rm = { i_status_bits_flags,
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assign r15_out_rm = { i_status_bits_flags,
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i_status_bits_irq_mask,
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i_status_bits_irq_mask,
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i_status_bits_firq_mask,
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i_status_bits_firq_mask,
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r15,
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r15,
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i_mode_exec};
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i_mode_exec};
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assign r15_out_rm_nxt = { i_status_bits_flags,
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assign r15_out_rm_nxt = { i_status_bits_flags,
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i_status_bits_irq_mask,
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i_status_bits_irq_mask,
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i_status_bits_firq_mask,
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i_status_bits_firq_mask,
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i_pc,
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i_pc,
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i_mode_exec};
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i_mode_exec};
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assign r15_out_rn = {6'd0, r15, 2'd0};
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assign r15_out_rn = {6'd0, r15, 2'd0};
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// ========================================================
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// ========================================================
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// Program Counter out
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// Program Counter out
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// ========================================================
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// ========================================================
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assign o_pc = r15_out_rn;
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assign o_pc = r15_out_rn;
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// ========================================================
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// ========================================================
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// Rm Selector
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// Rm Selector
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// ========================================================
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// ========================================================
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assign rm_out = reg_ram_m[rm_addr_reg];
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assign rm_out = reg_ram_m[rm_addr_reg];
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assign o_rm = rm_15 ? r15_out_rm :
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assign o_rm = rm_15 ? r15_out_rm :
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rm_out;
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rm_out;
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// ========================================================
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// ========================================================
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// Rds Selector
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// Rds Selector
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// ========================================================
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// ========================================================
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assign rds_out = reg_ram_ds[rds_addr_reg];
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assign rds_out = reg_ram_ds[rds_addr_reg];
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assign o_rs = rds_15 ? r15_out_rn :
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assign o_rs = rds_15 ? r15_out_rn :
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rds_out;
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rds_out;
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// ========================================================
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// ========================================================
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// Rd Selector
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// Rd Selector
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// ========================================================
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// ========================================================
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assign o_rd = rds_15 ? r15_out_rm_nxt :
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assign o_rd = rds_15 ? r15_out_rm_nxt :
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rds_out;
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rds_out;
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// ========================================================
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// ========================================================
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// Rn Selector
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// Rn Selector
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// ========================================================
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// ========================================================
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assign rn_out = reg_ram_n[rn_addr_reg];
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assign rn_out = reg_ram_n[rn_addr_reg];
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assign o_rn = rn_15 ? r15_out_rn :
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assign o_rn = rn_15 ? r15_out_rn :
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rn_out;
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rn_out;
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// ========================================================
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// ========================================================
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// Register Update
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// Register Update
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// ========================================================
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// ========================================================
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if (!i_fetch_stall)
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if (!i_fetch_stall)
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begin
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begin
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// Register write.
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// Register write.
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// Actually the code is synthesed as a syncronous ram
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// Actually the code is synthesed as a syncronous ram
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// with an additional pass-through multiplexor for
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// with an additional pass-through multiplexor for
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// read-when-write handling.
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// read-when-write handling.
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reg_ram_n[wr_addr] <= i_reg;
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reg_ram_n[wr_addr] <= i_reg;
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reg_ram_m[wr_addr] <= i_reg;
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reg_ram_m[wr_addr] <= i_reg;
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reg_ram_ds[wr_addr] <= i_reg;
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reg_ram_ds[wr_addr] <= i_reg;
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r15 <= i_pc_wen ? i_pc : r15;
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r15 <= i_pc_wen ? i_pc : r15;
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// The latching is actually implemented in a hard block.
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// The latching is actually implemented in a hard block.
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rn_addr_reg <= rn_addr;
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rn_addr_reg <= rn_addr;
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rm_addr_reg <= rm_addr;
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rm_addr_reg <= rm_addr;
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rds_addr_reg <= rds_addr;
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rds_addr_reg <= rds_addr;
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rn_15 <= i_rn_sel == 4'hF;
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rn_15 <= i_rn_sel == 4'hF;
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rm_15 <= i_rm_sel == 4'hF;
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rm_15 <= i_rm_sel == 4'hF;
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rds_15 <= i_rds_sel == 4'hF;
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rds_15 <= i_rds_sel == 4'hF;
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end
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end
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// ========================================================
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// ========================================================
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// Register mapping:
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// Register mapping:
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// ========================================================
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// ========================================================
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// 0xxxx : r0 - r14
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// 0xxxx : r0 - r14
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// 10xxx : r8_firq - r14_firq
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// 10xxx : r8_firq - r14_firq
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// 110xx : r13_irq - r14_irq
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// 110xx : r13_irq - r14_irq
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// 111xx : r13_svc - r14_svc
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// 111xx : r13_svc - r14_svc
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function [4:0] reg_addr;
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function [4:0] reg_addr;
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input [1:0] mode;
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input [1:0] mode;
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input [3:0] sel;
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input [3:0] sel;
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begin
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begin
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casez ({mode, sel}) // synthesis full_case parallel_case
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casez ({mode, sel}) // synthesis full_case parallel_case
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6'b??0???: reg_addr = {1'b0, sel}; // r0 - r7
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6'b??0???: reg_addr = {1'b0, sel}; // r0 - r7
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6'b1?1100: reg_addr = {1'b0, sel}; // irq and svc r12
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6'b1?1100: reg_addr = {1'b0, sel}; // irq and svc r12
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6'b001???: reg_addr = {1'b0, sel}; // user r8 - r14
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6'b001???: reg_addr = {1'b0, sel}; // user r8 - r14
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6'b011???: reg_addr = {2'b10, sel[2:0]}; // fiq r8-r14
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6'b011???: reg_addr = {2'b10, sel[2:0]}; // fiq r8-r14
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6'b1?10??: reg_addr = {1'b0, sel}; // irq and svc r8-r11
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6'b1?10??: reg_addr = {1'b0, sel}; // irq and svc r8-r11
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6'b101101: reg_addr = {3'b110, sel[1:0]}; // irq r13
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6'b101101: reg_addr = {3'b110, sel[1:0]}; // irq r13
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6'b101110: reg_addr = {3'b110, sel[1:0]}; // irq r14
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6'b101110: reg_addr = {3'b110, sel[1:0]}; // irq r14
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6'b101111: reg_addr = {3'b110, sel[1:0]}; // irq r15, just to make the case full
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6'b101111: reg_addr = {3'b110, sel[1:0]}; // irq r15, just to make the case full
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6'b111101: reg_addr = {3'b111, sel[1:0]}; // svc r13
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6'b111101: reg_addr = {3'b111, sel[1:0]}; // svc r13
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6'b111110: reg_addr = {3'b111, sel[1:0]}; // svc r14
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6'b111110: reg_addr = {3'b111, sel[1:0]}; // svc r14
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6'b111111: reg_addr = {3'b111, sel[1:0]}; // svc r15, just to make the case full
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6'b111111: reg_addr = {3'b111, sel[1:0]}; // svc r15, just to make the case full
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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// synthesis translate_off
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// synthesis translate_off
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// To be used as probes...
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// To be used as probes...
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wire [31:0] r0;
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wire [31:0] r0;
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wire [31:0] r1;
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wire [31:0] r1;
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wire [31:0] r2;
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wire [31:0] r2;
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wire [31:0] r3;
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wire [31:0] r3;
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wire [31:0] r4;
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wire [31:0] r4;
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wire [31:0] r5;
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wire [31:0] r5;
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wire [31:0] r6;
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wire [31:0] r6;
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wire [31:0] r7;
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wire [31:0] r7;
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wire [31:0] r8;
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wire [31:0] r8;
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wire [31:0] r9;
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wire [31:0] r9;
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wire [31:0] r10;
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wire [31:0] r10;
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wire [31:0] r11;
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wire [31:0] r11;
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wire [31:0] r12;
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wire [31:0] r12;
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wire [31:0] r13;
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wire [31:0] r13;
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wire [31:0] r14;
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wire [31:0] r14;
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wire [31:0] r13_svc;
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wire [31:0] r13_svc;
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wire [31:0] r14_svc;
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wire [31:0] r14_svc;
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wire [31:0] r13_irq;
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wire [31:0] r13_irq;
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wire [31:0] r14_irq;
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wire [31:0] r14_irq;
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wire [31:0] r8_firq;
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wire [31:0] r8_firq;
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wire [31:0] r9_firq;
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wire [31:0] r9_firq;
|
wire [31:0] r10_firq;
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wire [31:0] r10_firq;
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wire [31:0] r11_firq;
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wire [31:0] r11_firq;
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wire [31:0] r12_firq;
|
wire [31:0] r12_firq;
|
wire [31:0] r13_firq;
|
wire [31:0] r13_firq;
|
wire [31:0] r14_firq;
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wire [31:0] r14_firq;
|
wire [31:0] r0_out;
|
wire [31:0] r0_out;
|
wire [31:0] r1_out;
|
wire [31:0] r1_out;
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wire [31:0] r2_out;
|
wire [31:0] r2_out;
|
wire [31:0] r3_out;
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wire [31:0] r3_out;
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wire [31:0] r4_out;
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wire [31:0] r4_out;
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wire [31:0] r5_out;
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wire [31:0] r5_out;
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wire [31:0] r6_out;
|
wire [31:0] r6_out;
|
wire [31:0] r7_out;
|
wire [31:0] r7_out;
|
wire [31:0] r8_out;
|
wire [31:0] r8_out;
|
wire [31:0] r9_out;
|
wire [31:0] r9_out;
|
wire [31:0] r10_out;
|
wire [31:0] r10_out;
|
wire [31:0] r11_out;
|
wire [31:0] r11_out;
|
wire [31:0] r12_out;
|
wire [31:0] r12_out;
|
wire [31:0] r13_out;
|
wire [31:0] r13_out;
|
wire [31:0] r14_out;
|
wire [31:0] r14_out;
|
|
|
assign r0 = reg_ram_m[ 0];
|
assign r0 = reg_ram_m[ 0];
|
assign r1 = reg_ram_m[ 1];
|
assign r1 = reg_ram_m[ 1];
|
assign r2 = reg_ram_m[ 2];
|
assign r2 = reg_ram_m[ 2];
|
assign r3 = reg_ram_m[ 3];
|
assign r3 = reg_ram_m[ 3];
|
assign r4 = reg_ram_m[ 4];
|
assign r4 = reg_ram_m[ 4];
|
assign r5 = reg_ram_m[ 5];
|
assign r5 = reg_ram_m[ 5];
|
assign r6 = reg_ram_m[ 6];
|
assign r6 = reg_ram_m[ 6];
|
assign r7 = reg_ram_m[ 7];
|
assign r7 = reg_ram_m[ 7];
|
assign r8 = reg_ram_m[ 8];
|
assign r8 = reg_ram_m[ 8];
|
assign r9 = reg_ram_m[ 9];
|
assign r9 = reg_ram_m[ 9];
|
assign r10 = reg_ram_m[10];
|
assign r10 = reg_ram_m[10];
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assign r11 = reg_ram_m[11];
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assign r11 = reg_ram_m[11];
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assign r12 = reg_ram_m[12];
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assign r12 = reg_ram_m[12];
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assign r13 = reg_ram_m[13];
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assign r13 = reg_ram_m[13];
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assign r14 = reg_ram_m[14];
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assign r14 = reg_ram_m[14];
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assign r13_svc = reg_ram_m[29];
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assign r13_svc = reg_ram_m[29];
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assign r14_svc = reg_ram_m[30];
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assign r14_svc = reg_ram_m[30];
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assign r13_irq = reg_ram_m[25];
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assign r13_irq = reg_ram_m[25];
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assign r14_irq = reg_ram_m[26];
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assign r14_irq = reg_ram_m[26];
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assign r8_firq = reg_ram_m[16];
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assign r8_firq = reg_ram_m[16];
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assign r9_firq = reg_ram_m[17];
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assign r9_firq = reg_ram_m[17];
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assign r10_firq = reg_ram_m[18];
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assign r10_firq = reg_ram_m[18];
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assign r11_firq = reg_ram_m[19];
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assign r11_firq = reg_ram_m[19];
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assign r12_firq = reg_ram_m[20];
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assign r12_firq = reg_ram_m[20];
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assign r13_firq = reg_ram_m[21];
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assign r13_firq = reg_ram_m[21];
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assign r14_firq = reg_ram_m[22];
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assign r14_firq = reg_ram_m[22];
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assign r0_out = reg_ram_m[reg_addr(mode_exec, 0)];
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assign r0_out = reg_ram_m[reg_addr(mode_exec, 0)];
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assign r1_out = reg_ram_m[reg_addr(mode_exec, 1)];
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assign r1_out = reg_ram_m[reg_addr(mode_exec, 1)];
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assign r2_out = reg_ram_m[reg_addr(mode_exec, 2)];
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assign r2_out = reg_ram_m[reg_addr(mode_exec, 2)];
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assign r3_out = reg_ram_m[reg_addr(mode_exec, 3)];
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assign r3_out = reg_ram_m[reg_addr(mode_exec, 3)];
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assign r4_out = reg_ram_m[reg_addr(mode_exec, 4)];
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assign r4_out = reg_ram_m[reg_addr(mode_exec, 4)];
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assign r5_out = reg_ram_m[reg_addr(mode_exec, 5)];
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assign r5_out = reg_ram_m[reg_addr(mode_exec, 5)];
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assign r6_out = reg_ram_m[reg_addr(mode_exec, 6)];
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assign r6_out = reg_ram_m[reg_addr(mode_exec, 6)];
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assign r7_out = reg_ram_m[reg_addr(mode_exec, 7)];
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assign r7_out = reg_ram_m[reg_addr(mode_exec, 7)];
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assign r8_out = reg_ram_m[reg_addr(mode_exec, 8)];
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assign r8_out = reg_ram_m[reg_addr(mode_exec, 8)];
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assign r9_out = reg_ram_m[reg_addr(mode_exec, 9)];
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assign r9_out = reg_ram_m[reg_addr(mode_exec, 9)];
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assign r10_out = reg_ram_m[reg_addr(mode_exec, 10)];
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assign r10_out = reg_ram_m[reg_addr(mode_exec, 10)];
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assign r11_out = reg_ram_m[reg_addr(mode_exec, 11)];
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assign r11_out = reg_ram_m[reg_addr(mode_exec, 11)];
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assign r12_out = reg_ram_m[reg_addr(mode_exec, 12)];
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assign r12_out = reg_ram_m[reg_addr(mode_exec, 12)];
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assign r13_out = reg_ram_m[reg_addr(mode_exec, 13)];
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assign r13_out = reg_ram_m[reg_addr(mode_exec, 13)];
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assign r14_out = reg_ram_m[reg_addr(mode_exec, 14)];
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assign r14_out = reg_ram_m[reg_addr(mode_exec, 14)];
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// synthesis translate_on
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// synthesis translate_on
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endmodule
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endmodule
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