//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Register Bank for Amber 25 Core //
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// Register Bank for Amber 25 Core //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Contains 37 32-bit registers, 16 of which are visible //
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// Contains 37 32-bit registers, 16 of which are visible //
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// ina any one operating mode. Registers use real flipflops, //
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// ina any one operating mode. Registers use real flipflops, //
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// rather than SRAM. This makes sense for an FPGA //
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// rather than SRAM. This makes sense for an FPGA //
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// implementation, where flipflops are plentiful. //
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// implementation, where flipflops are plentiful. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module a25_register_bank (
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module a25_register_bank (
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input i_clk,
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input i_clk,
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input i_core_stall,
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input i_core_stall,
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input i_mem_stall,
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input i_mem_stall,
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input [1:0] i_mode_idec, // user, supervisor, irq_idec, firq_idec etc.
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input [1:0] i_mode_idec, // user, supervisor, irq_idec, firq_idec etc.
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// Used for register writes
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// Used for register writes
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input [1:0] i_mode_exec, // 1 periods delayed from i_mode_idec
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input [1:0] i_mode_exec, // 1 periods delayed from i_mode_idec
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// Used for register reads
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// Used for register reads
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input [3:0] i_mode_rds_exec, // Use one-hot version specifically for rds,
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input [3:0] i_mode_rds_exec, // Use one-hot version specifically for rds,
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// includes i_user_mode_regs_store
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// includes i_user_mode_regs_store
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input i_firq_not_user_mode,
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input i_firq_not_user_mode,
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input [3:0] i_rm_sel,
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input [3:0] i_rm_sel,
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input [3:0] i_rs_sel,
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input [3:0] i_rs_sel,
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input [3:0] i_rn_sel,
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input [3:0] i_rn_sel,
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input i_pc_wen,
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input i_pc_wen,
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input [14:0] i_reg_bank_wen,
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input [14:0] i_reg_bank_wen,
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input [23:0] i_pc, // program counter [25:2]
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input [23:0] i_pc, // program counter [25:2]
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input [31:0] i_reg,
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input [31:0] i_reg,
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input [31:0] i_wb_read_data,
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input [31:0] i_wb_read_data,
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input i_wb_read_data_valid,
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input i_wb_read_data_valid,
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input [3:0] i_wb_read_data_rd,
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input [3:0] i_wb_read_data_rd,
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input [1:0] i_wb_mode,
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input [1:0] i_wb_mode,
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input [3:0] i_status_bits_flags,
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input [3:0] i_status_bits_flags,
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input i_status_bits_irq_mask,
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input i_status_bits_irq_mask,
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input i_status_bits_firq_mask,
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input i_status_bits_firq_mask,
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output [31:0] o_rm,
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output [31:0] o_rm,
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output reg [31:0] o_rs,
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output reg [31:0] o_rs,
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output reg [31:0] o_rd,
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output reg [31:0] o_rd,
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output [31:0] o_rn,
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output [31:0] o_rn,
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output [31:0] o_pc
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output [31:0] o_pc
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);
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);
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`include "a25_localparams.v"
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`include "a25_localparams.vh"
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`include "a25_functions.v"
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`include "a25_functions.vh"
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// User Mode Registers
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// User Mode Registers
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reg [31:0] r0 = 32'hdead_beef;
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reg [31:0] r0 = 32'hdead_beef;
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reg [31:0] r1 = 32'hdead_beef;
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reg [31:0] r1 = 32'hdead_beef;
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reg [31:0] r2 = 32'hdead_beef;
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reg [31:0] r2 = 32'hdead_beef;
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reg [31:0] r3 = 32'hdead_beef;
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reg [31:0] r3 = 32'hdead_beef;
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reg [31:0] r4 = 32'hdead_beef;
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reg [31:0] r4 = 32'hdead_beef;
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reg [31:0] r5 = 32'hdead_beef;
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reg [31:0] r5 = 32'hdead_beef;
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reg [31:0] r6 = 32'hdead_beef;
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reg [31:0] r6 = 32'hdead_beef;
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reg [31:0] r7 = 32'hdead_beef;
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reg [31:0] r7 = 32'hdead_beef;
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reg [31:0] r8 = 32'hdead_beef;
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reg [31:0] r8 = 32'hdead_beef;
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reg [31:0] r9 = 32'hdead_beef;
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reg [31:0] r9 = 32'hdead_beef;
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reg [31:0] r10 = 32'hdead_beef;
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reg [31:0] r10 = 32'hdead_beef;
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reg [31:0] r11 = 32'hdead_beef;
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reg [31:0] r11 = 32'hdead_beef;
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reg [31:0] r12 = 32'hdead_beef;
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reg [31:0] r12 = 32'hdead_beef;
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reg [31:0] r13 = 32'hdead_beef;
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reg [31:0] r13 = 32'hdead_beef;
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reg [31:0] r14 = 32'hdead_beef;
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reg [31:0] r14 = 32'hdead_beef;
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reg [23:0] r15 = 24'hc0_ffee;
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reg [23:0] r15 = 24'hc0_ffee;
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wire [31:0] r0_out;
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wire [31:0] r0_out;
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wire [31:0] r1_out;
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wire [31:0] r1_out;
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wire [31:0] r2_out;
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wire [31:0] r2_out;
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wire [31:0] r3_out;
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wire [31:0] r3_out;
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wire [31:0] r4_out;
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wire [31:0] r4_out;
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wire [31:0] r5_out;
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wire [31:0] r5_out;
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wire [31:0] r6_out;
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wire [31:0] r6_out;
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wire [31:0] r7_out;
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wire [31:0] r7_out;
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wire [31:0] r8_out;
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wire [31:0] r8_out;
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wire [31:0] r9_out;
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wire [31:0] r9_out;
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wire [31:0] r10_out;
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wire [31:0] r10_out;
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wire [31:0] r11_out;
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wire [31:0] r11_out;
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wire [31:0] r12_out;
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wire [31:0] r12_out;
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wire [31:0] r13_out;
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wire [31:0] r13_out;
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wire [31:0] r14_out;
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wire [31:0] r14_out;
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wire [31:0] r15_out_rm;
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wire [31:0] r15_out_rm;
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wire [31:0] r15_out_rm_nxt;
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wire [31:0] r15_out_rm_nxt;
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wire [31:0] r15_out_rn;
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wire [31:0] r15_out_rn;
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wire [31:0] r8_rds;
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wire [31:0] r8_rds;
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wire [31:0] r9_rds;
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wire [31:0] r9_rds;
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wire [31:0] r10_rds;
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wire [31:0] r10_rds;
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wire [31:0] r11_rds;
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wire [31:0] r11_rds;
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wire [31:0] r12_rds;
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wire [31:0] r12_rds;
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wire [31:0] r13_rds;
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wire [31:0] r13_rds;
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wire [31:0] r14_rds;
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wire [31:0] r14_rds;
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// Supervisor Mode Registers
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// Supervisor Mode Registers
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reg [31:0] r13_svc = 32'hdead_beef;
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reg [31:0] r13_svc = 32'hdead_beef;
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reg [31:0] r14_svc = 32'hdead_beef;
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reg [31:0] r14_svc = 32'hdead_beef;
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// Interrupt Mode Registers
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// Interrupt Mode Registers
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reg [31:0] r13_irq = 32'hdead_beef;
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reg [31:0] r13_irq = 32'hdead_beef;
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reg [31:0] r14_irq = 32'hdead_beef;
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reg [31:0] r14_irq = 32'hdead_beef;
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// Fast Interrupt Mode Registers
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// Fast Interrupt Mode Registers
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reg [31:0] r8_firq = 32'hdead_beef;
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reg [31:0] r8_firq = 32'hdead_beef;
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reg [31:0] r9_firq = 32'hdead_beef;
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reg [31:0] r9_firq = 32'hdead_beef;
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reg [31:0] r10_firq = 32'hdead_beef;
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reg [31:0] r10_firq = 32'hdead_beef;
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reg [31:0] r11_firq = 32'hdead_beef;
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reg [31:0] r11_firq = 32'hdead_beef;
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reg [31:0] r12_firq = 32'hdead_beef;
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reg [31:0] r12_firq = 32'hdead_beef;
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reg [31:0] r13_firq = 32'hdead_beef;
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reg [31:0] r13_firq = 32'hdead_beef;
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reg [31:0] r14_firq = 32'hdead_beef;
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reg [31:0] r14_firq = 32'hdead_beef;
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wire usr_exec;
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wire usr_exec;
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wire svc_exec;
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wire svc_exec;
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wire irq_exec;
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wire irq_exec;
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wire firq_exec;
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wire firq_exec;
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wire usr_idec;
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wire usr_idec;
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wire svc_idec;
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wire svc_idec;
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wire irq_idec;
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wire irq_idec;
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wire firq_idec;
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wire firq_idec;
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wire [14:0] read_data_wen;
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wire [14:0] read_data_wen;
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wire [14:0] reg_bank_wen_c;
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wire [14:0] reg_bank_wen_c;
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wire pc_wen_c;
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wire pc_wen_c;
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wire pc_dmem_wen;
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wire pc_dmem_wen;
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// Write Enables from execute stage
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// Write Enables from execute stage
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assign usr_idec = i_mode_idec == USR;
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assign usr_idec = i_mode_idec == USR;
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assign svc_idec = i_mode_idec == SVC;
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assign svc_idec = i_mode_idec == SVC;
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assign irq_idec = i_mode_idec == IRQ;
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assign irq_idec = i_mode_idec == IRQ;
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// pre-encoded in decode stage to speed up long path
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// pre-encoded in decode stage to speed up long path
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assign firq_idec = i_firq_not_user_mode;
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assign firq_idec = i_firq_not_user_mode;
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// Read Enables from stage 1 (fetch)
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// Read Enables from stage 1 (fetch)
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assign usr_exec = i_mode_exec == USR;
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assign usr_exec = i_mode_exec == USR;
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assign svc_exec = i_mode_exec == SVC;
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assign svc_exec = i_mode_exec == SVC;
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assign irq_exec = i_mode_exec == IRQ;
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assign irq_exec = i_mode_exec == IRQ;
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assign firq_exec = i_mode_exec == FIRQ;
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assign firq_exec = i_mode_exec == FIRQ;
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assign read_data_wen = {15{i_wb_read_data_valid & ~i_mem_stall}} & decode (i_wb_read_data_rd);
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assign read_data_wen = {15{i_wb_read_data_valid & ~i_mem_stall}} & decode (i_wb_read_data_rd);
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assign reg_bank_wen_c = {15{~i_core_stall}} & i_reg_bank_wen;
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assign reg_bank_wen_c = {15{~i_core_stall}} & i_reg_bank_wen;
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assign pc_wen_c = ~i_core_stall & i_pc_wen;
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assign pc_wen_c = ~i_core_stall & i_pc_wen;
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assign pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_read_data_rd == 4'd15;
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assign pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_read_data_rd == 4'd15;
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// ========================================================
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// ========================================================
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// Register Update
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// Register Update
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// ========================================================
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// ========================================================
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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begin
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begin
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// these registers are used in all modes
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// these registers are used in all modes
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r0 <= reg_bank_wen_c[0 ] ? i_reg : read_data_wen[0 ] ? i_wb_read_data : r0;
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r0 <= reg_bank_wen_c[0 ] ? i_reg : read_data_wen[0 ] ? i_wb_read_data : r0;
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r1 <= reg_bank_wen_c[1 ] ? i_reg : read_data_wen[1 ] ? i_wb_read_data : r1;
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r1 <= reg_bank_wen_c[1 ] ? i_reg : read_data_wen[1 ] ? i_wb_read_data : r1;
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r2 <= reg_bank_wen_c[2 ] ? i_reg : read_data_wen[2 ] ? i_wb_read_data : r2;
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r2 <= reg_bank_wen_c[2 ] ? i_reg : read_data_wen[2 ] ? i_wb_read_data : r2;
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r3 <= reg_bank_wen_c[3 ] ? i_reg : read_data_wen[3 ] ? i_wb_read_data : r3;
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r3 <= reg_bank_wen_c[3 ] ? i_reg : read_data_wen[3 ] ? i_wb_read_data : r3;
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r4 <= reg_bank_wen_c[4 ] ? i_reg : read_data_wen[4 ] ? i_wb_read_data : r4;
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r4 <= reg_bank_wen_c[4 ] ? i_reg : read_data_wen[4 ] ? i_wb_read_data : r4;
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r5 <= reg_bank_wen_c[5 ] ? i_reg : read_data_wen[5 ] ? i_wb_read_data : r5;
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r5 <= reg_bank_wen_c[5 ] ? i_reg : read_data_wen[5 ] ? i_wb_read_data : r5;
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r6 <= reg_bank_wen_c[6 ] ? i_reg : read_data_wen[6 ] ? i_wb_read_data : r6;
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r6 <= reg_bank_wen_c[6 ] ? i_reg : read_data_wen[6 ] ? i_wb_read_data : r6;
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r7 <= reg_bank_wen_c[7 ] ? i_reg : read_data_wen[7 ] ? i_wb_read_data : r7;
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r7 <= reg_bank_wen_c[7 ] ? i_reg : read_data_wen[7 ] ? i_wb_read_data : r7;
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// these registers are used in all modes, except fast irq
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// these registers are used in all modes, except fast irq
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r8 <= reg_bank_wen_c[8 ] && !firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode != FIRQ ? i_wb_read_data : r8;
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r8 <= reg_bank_wen_c[8 ] && !firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode != FIRQ ? i_wb_read_data : r8;
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r9 <= reg_bank_wen_c[9 ] && !firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode != FIRQ ? i_wb_read_data : r9;
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r9 <= reg_bank_wen_c[9 ] && !firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode != FIRQ ? i_wb_read_data : r9;
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r10 <= reg_bank_wen_c[10] && !firq_idec ? i_reg : read_data_wen[10] && i_wb_mode != FIRQ ? i_wb_read_data : r10;
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r10 <= reg_bank_wen_c[10] && !firq_idec ? i_reg : read_data_wen[10] && i_wb_mode != FIRQ ? i_wb_read_data : r10;
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r11 <= reg_bank_wen_c[11] && !firq_idec ? i_reg : read_data_wen[11] && i_wb_mode != FIRQ ? i_wb_read_data : r11;
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r11 <= reg_bank_wen_c[11] && !firq_idec ? i_reg : read_data_wen[11] && i_wb_mode != FIRQ ? i_wb_read_data : r11;
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r12 <= reg_bank_wen_c[12] && !firq_idec ? i_reg : read_data_wen[12] && i_wb_mode != FIRQ ? i_wb_read_data : r12;
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r12 <= reg_bank_wen_c[12] && !firq_idec ? i_reg : read_data_wen[12] && i_wb_mode != FIRQ ? i_wb_read_data : r12;
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// these registers are used in fast irq mode
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// these registers are used in fast irq mode
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r8_firq <= reg_bank_wen_c[8 ] && firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode == FIRQ ? i_wb_read_data : r8_firq;
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r8_firq <= reg_bank_wen_c[8 ] && firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode == FIRQ ? i_wb_read_data : r8_firq;
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r9_firq <= reg_bank_wen_c[9 ] && firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode == FIRQ ? i_wb_read_data : r9_firq;
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r9_firq <= reg_bank_wen_c[9 ] && firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode == FIRQ ? i_wb_read_data : r9_firq;
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r10_firq <= reg_bank_wen_c[10] && firq_idec ? i_reg : read_data_wen[10] && i_wb_mode == FIRQ ? i_wb_read_data : r10_firq;
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r10_firq <= reg_bank_wen_c[10] && firq_idec ? i_reg : read_data_wen[10] && i_wb_mode == FIRQ ? i_wb_read_data : r10_firq;
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r11_firq <= reg_bank_wen_c[11] && firq_idec ? i_reg : read_data_wen[11] && i_wb_mode == FIRQ ? i_wb_read_data : r11_firq;
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r11_firq <= reg_bank_wen_c[11] && firq_idec ? i_reg : read_data_wen[11] && i_wb_mode == FIRQ ? i_wb_read_data : r11_firq;
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r12_firq <= reg_bank_wen_c[12] && firq_idec ? i_reg : read_data_wen[12] && i_wb_mode == FIRQ ? i_wb_read_data : r12_firq;
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r12_firq <= reg_bank_wen_c[12] && firq_idec ? i_reg : read_data_wen[12] && i_wb_mode == FIRQ ? i_wb_read_data : r12_firq;
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// these registers are used in user mode
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// these registers are used in user mode
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r13 <= reg_bank_wen_c[13] && usr_idec ? i_reg : read_data_wen[13] && i_wb_mode == USR ? i_wb_read_data : r13;
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r13 <= reg_bank_wen_c[13] && usr_idec ? i_reg : read_data_wen[13] && i_wb_mode == USR ? i_wb_read_data : r13;
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r14 <= reg_bank_wen_c[14] && usr_idec ? i_reg : read_data_wen[14] && i_wb_mode == USR ? i_wb_read_data : r14;
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r14 <= reg_bank_wen_c[14] && usr_idec ? i_reg : read_data_wen[14] && i_wb_mode == USR ? i_wb_read_data : r14;
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// these registers are used in supervisor mode
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// these registers are used in supervisor mode
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r13_svc <= reg_bank_wen_c[13] && svc_idec ? i_reg : read_data_wen[13] && i_wb_mode == SVC ? i_wb_read_data : r13_svc;
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r13_svc <= reg_bank_wen_c[13] && svc_idec ? i_reg : read_data_wen[13] && i_wb_mode == SVC ? i_wb_read_data : r13_svc;
|
r14_svc <= reg_bank_wen_c[14] && svc_idec ? i_reg : read_data_wen[14] && i_wb_mode == SVC ? i_wb_read_data : r14_svc;
|
r14_svc <= reg_bank_wen_c[14] && svc_idec ? i_reg : read_data_wen[14] && i_wb_mode == SVC ? i_wb_read_data : r14_svc;
|
|
|
// these registers are used in irq mode
|
// these registers are used in irq mode
|
r13_irq <= reg_bank_wen_c[13] && irq_idec ? i_reg : read_data_wen[13] && i_wb_mode == IRQ ? i_wb_read_data : r13_irq;
|
r13_irq <= reg_bank_wen_c[13] && irq_idec ? i_reg : read_data_wen[13] && i_wb_mode == IRQ ? i_wb_read_data : r13_irq;
|
r14_irq <= (reg_bank_wen_c[14] && irq_idec) ? i_reg : read_data_wen[14] && i_wb_mode == IRQ ? i_wb_read_data : r14_irq;
|
r14_irq <= (reg_bank_wen_c[14] && irq_idec) ? i_reg : read_data_wen[14] && i_wb_mode == IRQ ? i_wb_read_data : r14_irq;
|
|
|
// these registers are used in fast irq mode
|
// these registers are used in fast irq mode
|
r13_firq <= reg_bank_wen_c[13] && firq_idec ? i_reg : read_data_wen[13] && i_wb_mode == FIRQ ? i_wb_read_data : r13_firq;
|
r13_firq <= reg_bank_wen_c[13] && firq_idec ? i_reg : read_data_wen[13] && i_wb_mode == FIRQ ? i_wb_read_data : r13_firq;
|
r14_firq <= reg_bank_wen_c[14] && firq_idec ? i_reg : read_data_wen[14] && i_wb_mode == FIRQ ? i_wb_read_data : r14_firq;
|
r14_firq <= reg_bank_wen_c[14] && firq_idec ? i_reg : read_data_wen[14] && i_wb_mode == FIRQ ? i_wb_read_data : r14_firq;
|
|
|
// these registers are used in all modes
|
// these registers are used in all modes
|
r15 <= pc_wen_c ? i_pc : pc_dmem_wen ? i_wb_read_data[25:2] : r15;
|
r15 <= pc_wen_c ? i_pc : pc_dmem_wen ? i_wb_read_data[25:2] : r15;
|
end
|
end
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Register Read based on Mode
|
// Register Read based on Mode
|
// ========================================================
|
// ========================================================
|
assign r0_out = r0;
|
assign r0_out = r0;
|
assign r1_out = r1;
|
assign r1_out = r1;
|
assign r2_out = r2;
|
assign r2_out = r2;
|
assign r3_out = r3;
|
assign r3_out = r3;
|
assign r4_out = r4;
|
assign r4_out = r4;
|
assign r5_out = r5;
|
assign r5_out = r5;
|
assign r6_out = r6;
|
assign r6_out = r6;
|
assign r7_out = r7;
|
assign r7_out = r7;
|
|
|
assign r8_out = firq_exec ? r8_firq : r8;
|
assign r8_out = firq_exec ? r8_firq : r8;
|
assign r9_out = firq_exec ? r9_firq : r9;
|
assign r9_out = firq_exec ? r9_firq : r9;
|
assign r10_out = firq_exec ? r10_firq : r10;
|
assign r10_out = firq_exec ? r10_firq : r10;
|
assign r11_out = firq_exec ? r11_firq : r11;
|
assign r11_out = firq_exec ? r11_firq : r11;
|
assign r12_out = firq_exec ? r12_firq : r12;
|
assign r12_out = firq_exec ? r12_firq : r12;
|
|
|
assign r13_out = usr_exec ? r13 :
|
assign r13_out = usr_exec ? r13 :
|
svc_exec ? r13_svc :
|
svc_exec ? r13_svc :
|
irq_exec ? r13_irq :
|
irq_exec ? r13_irq :
|
r13_firq ;
|
r13_firq ;
|
|
|
assign r14_out = usr_exec ? r14 :
|
assign r14_out = usr_exec ? r14 :
|
svc_exec ? r14_svc :
|
svc_exec ? r14_svc :
|
irq_exec ? r14_irq :
|
irq_exec ? r14_irq :
|
r14_firq ;
|
r14_firq ;
|
|
|
|
|
assign r15_out_rm = { i_status_bits_flags,
|
assign r15_out_rm = { i_status_bits_flags,
|
i_status_bits_irq_mask,
|
i_status_bits_irq_mask,
|
i_status_bits_firq_mask,
|
i_status_bits_firq_mask,
|
r15,
|
r15,
|
i_mode_exec};
|
i_mode_exec};
|
|
|
assign r15_out_rm_nxt = { i_status_bits_flags,
|
assign r15_out_rm_nxt = { i_status_bits_flags,
|
i_status_bits_irq_mask,
|
i_status_bits_irq_mask,
|
i_status_bits_firq_mask,
|
i_status_bits_firq_mask,
|
i_pc,
|
i_pc,
|
i_mode_exec};
|
i_mode_exec};
|
|
|
assign r15_out_rn = {6'd0, r15, 2'd0};
|
assign r15_out_rn = {6'd0, r15, 2'd0};
|
|
|
|
|
// rds outputs
|
// rds outputs
|
assign r8_rds = i_mode_rds_exec[OH_FIRQ] ? r8_firq : r8;
|
assign r8_rds = i_mode_rds_exec[OH_FIRQ] ? r8_firq : r8;
|
assign r9_rds = i_mode_rds_exec[OH_FIRQ] ? r9_firq : r9;
|
assign r9_rds = i_mode_rds_exec[OH_FIRQ] ? r9_firq : r9;
|
assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
|
assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
|
assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
|
assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
|
assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
|
assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
|
|
|
assign r13_rds = i_mode_rds_exec[OH_USR] ? r13 :
|
assign r13_rds = i_mode_rds_exec[OH_USR] ? r13 :
|
i_mode_rds_exec[OH_SVC] ? r13_svc :
|
i_mode_rds_exec[OH_SVC] ? r13_svc :
|
i_mode_rds_exec[OH_IRQ] ? r13_irq :
|
i_mode_rds_exec[OH_IRQ] ? r13_irq :
|
r13_firq ;
|
r13_firq ;
|
|
|
assign r14_rds = i_mode_rds_exec[OH_USR] ? r14 :
|
assign r14_rds = i_mode_rds_exec[OH_USR] ? r14 :
|
i_mode_rds_exec[OH_SVC] ? r14_svc :
|
i_mode_rds_exec[OH_SVC] ? r14_svc :
|
i_mode_rds_exec[OH_IRQ] ? r14_irq :
|
i_mode_rds_exec[OH_IRQ] ? r14_irq :
|
r14_firq ;
|
r14_firq ;
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Program Counter out
|
// Program Counter out
|
// ========================================================
|
// ========================================================
|
assign o_pc = r15_out_rn;
|
assign o_pc = r15_out_rn;
|
|
|
// ========================================================
|
// ========================================================
|
// Rm Selector
|
// Rm Selector
|
// ========================================================
|
// ========================================================
|
assign o_rm = i_rm_sel == 4'd0 ? r0_out :
|
assign o_rm = i_rm_sel == 4'd0 ? r0_out :
|
i_rm_sel == 4'd1 ? r1_out :
|
i_rm_sel == 4'd1 ? r1_out :
|
i_rm_sel == 4'd2 ? r2_out :
|
i_rm_sel == 4'd2 ? r2_out :
|
i_rm_sel == 4'd3 ? r3_out :
|
i_rm_sel == 4'd3 ? r3_out :
|
i_rm_sel == 4'd4 ? r4_out :
|
i_rm_sel == 4'd4 ? r4_out :
|
i_rm_sel == 4'd5 ? r5_out :
|
i_rm_sel == 4'd5 ? r5_out :
|
i_rm_sel == 4'd6 ? r6_out :
|
i_rm_sel == 4'd6 ? r6_out :
|
i_rm_sel == 4'd7 ? r7_out :
|
i_rm_sel == 4'd7 ? r7_out :
|
i_rm_sel == 4'd8 ? r8_out :
|
i_rm_sel == 4'd8 ? r8_out :
|
i_rm_sel == 4'd9 ? r9_out :
|
i_rm_sel == 4'd9 ? r9_out :
|
i_rm_sel == 4'd10 ? r10_out :
|
i_rm_sel == 4'd10 ? r10_out :
|
i_rm_sel == 4'd11 ? r11_out :
|
i_rm_sel == 4'd11 ? r11_out :
|
i_rm_sel == 4'd12 ? r12_out :
|
i_rm_sel == 4'd12 ? r12_out :
|
i_rm_sel == 4'd13 ? r13_out :
|
i_rm_sel == 4'd13 ? r13_out :
|
i_rm_sel == 4'd14 ? r14_out :
|
i_rm_sel == 4'd14 ? r14_out :
|
r15_out_rm ;
|
r15_out_rm ;
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Rds Selector
|
// Rds Selector
|
// ========================================================
|
// ========================================================
|
always @*
|
always @*
|
case ( i_rs_sel )
|
case ( i_rs_sel )
|
4'd0 : o_rs = r0_out ;
|
4'd0 : o_rs = r0_out ;
|
4'd1 : o_rs = r1_out ;
|
4'd1 : o_rs = r1_out ;
|
4'd2 : o_rs = r2_out ;
|
4'd2 : o_rs = r2_out ;
|
4'd3 : o_rs = r3_out ;
|
4'd3 : o_rs = r3_out ;
|
4'd4 : o_rs = r4_out ;
|
4'd4 : o_rs = r4_out ;
|
4'd5 : o_rs = r5_out ;
|
4'd5 : o_rs = r5_out ;
|
4'd6 : o_rs = r6_out ;
|
4'd6 : o_rs = r6_out ;
|
4'd7 : o_rs = r7_out ;
|
4'd7 : o_rs = r7_out ;
|
4'd8 : o_rs = r8_rds ;
|
4'd8 : o_rs = r8_rds ;
|
4'd9 : o_rs = r9_rds ;
|
4'd9 : o_rs = r9_rds ;
|
4'd10 : o_rs = r10_rds ;
|
4'd10 : o_rs = r10_rds ;
|
4'd11 : o_rs = r11_rds ;
|
4'd11 : o_rs = r11_rds ;
|
4'd12 : o_rs = r12_rds ;
|
4'd12 : o_rs = r12_rds ;
|
4'd13 : o_rs = r13_rds ;
|
4'd13 : o_rs = r13_rds ;
|
4'd14 : o_rs = r14_rds ;
|
4'd14 : o_rs = r14_rds ;
|
default: o_rs = r15_out_rn ;
|
default: o_rs = r15_out_rn ;
|
endcase
|
endcase
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Rd Selector
|
// Rd Selector
|
// ========================================================
|
// ========================================================
|
always @*
|
always @*
|
case ( i_rs_sel )
|
case ( i_rs_sel )
|
4'd0 : o_rd = r0_out ;
|
4'd0 : o_rd = r0_out ;
|
4'd1 : o_rd = r1_out ;
|
4'd1 : o_rd = r1_out ;
|
4'd2 : o_rd = r2_out ;
|
4'd2 : o_rd = r2_out ;
|
4'd3 : o_rd = r3_out ;
|
4'd3 : o_rd = r3_out ;
|
4'd4 : o_rd = r4_out ;
|
4'd4 : o_rd = r4_out ;
|
4'd5 : o_rd = r5_out ;
|
4'd5 : o_rd = r5_out ;
|
4'd6 : o_rd = r6_out ;
|
4'd6 : o_rd = r6_out ;
|
4'd7 : o_rd = r7_out ;
|
4'd7 : o_rd = r7_out ;
|
4'd8 : o_rd = r8_rds ;
|
4'd8 : o_rd = r8_rds ;
|
4'd9 : o_rd = r9_rds ;
|
4'd9 : o_rd = r9_rds ;
|
4'd10 : o_rd = r10_rds ;
|
4'd10 : o_rd = r10_rds ;
|
4'd11 : o_rd = r11_rds ;
|
4'd11 : o_rd = r11_rds ;
|
4'd12 : o_rd = r12_rds ;
|
4'd12 : o_rd = r12_rds ;
|
4'd13 : o_rd = r13_rds ;
|
4'd13 : o_rd = r13_rds ;
|
4'd14 : o_rd = r14_rds ;
|
4'd14 : o_rd = r14_rds ;
|
default: o_rd = r15_out_rm_nxt ;
|
default: o_rd = r15_out_rm_nxt ;
|
endcase
|
endcase
|
|
|
|
|
// ========================================================
|
// ========================================================
|
// Rn Selector
|
// Rn Selector
|
// ========================================================
|
// ========================================================
|
assign o_rn = i_rn_sel == 4'd0 ? r0_out :
|
assign o_rn = i_rn_sel == 4'd0 ? r0_out :
|
i_rn_sel == 4'd1 ? r1_out :
|
i_rn_sel == 4'd1 ? r1_out :
|
i_rn_sel == 4'd2 ? r2_out :
|
i_rn_sel == 4'd2 ? r2_out :
|
i_rn_sel == 4'd3 ? r3_out :
|
i_rn_sel == 4'd3 ? r3_out :
|
i_rn_sel == 4'd4 ? r4_out :
|
i_rn_sel == 4'd4 ? r4_out :
|
i_rn_sel == 4'd5 ? r5_out :
|
i_rn_sel == 4'd5 ? r5_out :
|
i_rn_sel == 4'd6 ? r6_out :
|
i_rn_sel == 4'd6 ? r6_out :
|
i_rn_sel == 4'd7 ? r7_out :
|
i_rn_sel == 4'd7 ? r7_out :
|
i_rn_sel == 4'd8 ? r8_out :
|
i_rn_sel == 4'd8 ? r8_out :
|
i_rn_sel == 4'd9 ? r9_out :
|
i_rn_sel == 4'd9 ? r9_out :
|
i_rn_sel == 4'd10 ? r10_out :
|
i_rn_sel == 4'd10 ? r10_out :
|
i_rn_sel == 4'd11 ? r11_out :
|
i_rn_sel == 4'd11 ? r11_out :
|
i_rn_sel == 4'd12 ? r12_out :
|
i_rn_sel == 4'd12 ? r12_out :
|
i_rn_sel == 4'd13 ? r13_out :
|
i_rn_sel == 4'd13 ? r13_out :
|
i_rn_sel == 4'd14 ? r14_out :
|
i_rn_sel == 4'd14 ? r14_out :
|
r15_out_rn ;
|
r15_out_rn ;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|