//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Test Module //
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// Test Module //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Contains a random number generator and a couple of timers //
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// Contains a random number generator and a couple of timers //
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// that connect to interrupt lines. Used for testing the //
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// that connect to interrupt lines. Used for testing the //
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// ssytem. //
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// ssytem. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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module test_module #(
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module test_module #(
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parameter WB_DWIDTH = 32,
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parameter WB_DWIDTH = 32,
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parameter WB_SWIDTH = 4
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parameter WB_SWIDTH = 4
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)(
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)(
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input i_clk,
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input i_clk,
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|
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output o_irq,
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output o_irq,
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output o_firq,
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output o_firq,
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output o_mem_ctrl, // 0=128MB, 1=32MB
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output o_mem_ctrl, // 0=128MB, 1=32MB
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input [31:0] i_wb_adr,
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input [31:0] i_wb_adr,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input [WB_SWIDTH-1:0] i_wb_sel,
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input i_wb_we,
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input i_wb_we,
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output [WB_DWIDTH-1:0] o_wb_dat,
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output [WB_DWIDTH-1:0] o_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input [WB_DWIDTH-1:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_ack,
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output o_wb_err,
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output o_wb_err,
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output [3:0] o_led,
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output [3:0] o_led,
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output o_phy_rst_n
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output o_phy_rst_n
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|
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);
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);
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`include "register_addresses.v"
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`include "register_addresses.vh"
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reg [7:0] firq_timer = 'd0;
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reg [7:0] firq_timer = 'd0;
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reg [7:0] irq_timer = 'd0;
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reg [7:0] irq_timer = 'd0;
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reg [7:0] random_num = 8'hf3;
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reg [7:0] random_num = 8'hf3;
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//synopsys translate_off
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//synopsys translate_off
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reg [1:0] tb_uart_control_reg = 'd0;
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reg [1:0] tb_uart_control_reg = 'd0;
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reg [1:0] tb_uart_status_reg = 'd0;
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reg [1:0] tb_uart_status_reg = 'd0;
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reg tb_uart_push = 'd0;
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reg tb_uart_push = 'd0;
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reg [7:0] tb_uart_txd_reg = 'd0;
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reg [7:0] tb_uart_txd_reg = 'd0;
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//synopsys translate_on
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//synopsys translate_on
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reg [2:0] sim_ctrl_reg = 'd0; // 0 = fpga, other values for simulations
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reg [2:0] sim_ctrl_reg = 'd0; // 0 = fpga, other values for simulations
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reg mem_ctrl_reg = 'd0; // 0 = 128MB, 1 = 32MB main memory
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reg mem_ctrl_reg = 'd0; // 0 = 128MB, 1 = 32MB main memory
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reg [31:0] test_status_reg = 'd0;
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reg [31:0] test_status_reg = 'd0;
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reg test_status_set = 'd0; // used to terminate tests
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reg test_status_set = 'd0; // used to terminate tests
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reg [31:0] cycles_reg = 'd0;
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reg [31:0] cycles_reg = 'd0;
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|
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wire wb_start_write;
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wire wb_start_write;
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wire wb_start_read;
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wire wb_start_read;
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reg wb_start_read_d1 = 'd0;
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reg wb_start_read_d1 = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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reg [31:0] wb_rdata32 = 'd0;
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wire [31:0] wb_wdata32;
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wire [31:0] wb_wdata32;
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reg [3:0] led_reg = 'd0;
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reg [3:0] led_reg = 'd0;
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reg phy_rst_reg = 'd0;
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reg phy_rst_reg = 'd0;
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// Can't start a write while a read is completing. The ack for the read cycle
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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// needs to be sent first
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
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always @( posedge i_clk )
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always @( posedge i_clk )
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wb_start_read_d1 <= wb_start_read;
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wb_start_read_d1 <= wb_start_read;
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
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assign o_wb_err = 1'd0;
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assign o_wb_err = 1'd0;
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assign o_mem_ctrl = mem_ctrl_reg;
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assign o_mem_ctrl = mem_ctrl_reg;
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assign o_led = led_reg;
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assign o_led = led_reg;
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assign o_phy_rst_n = phy_rst_reg;
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assign o_phy_rst_n = phy_rst_reg;
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generate
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generate
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if (WB_DWIDTH == 128)
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if (WB_DWIDTH == 128)
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begin : wb128
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begin : wb128
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
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i_wb_dat[ 31: 0] ;
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i_wb_dat[ 31: 0] ;
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assign o_wb_dat = {4{wb_rdata32}};
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assign o_wb_dat = {4{wb_rdata32}};
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end
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end
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else
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else
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begin : wb32
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begin : wb32
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assign wb_wdata32 = i_wb_dat;
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assign wb_wdata32 = i_wb_dat;
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assign o_wb_dat = wb_rdata32;
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assign o_wb_dat = wb_rdata32;
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end
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end
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endgenerate
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endgenerate
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// ========================================================
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// ========================================================
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// Register Reads
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// Register Reads
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_read )
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if ( wb_start_read )
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case ( i_wb_adr[15:0] )
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case ( i_wb_adr[15:0] )
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AMBER_TEST_STATUS: wb_rdata32 <= test_status_reg;
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AMBER_TEST_STATUS: wb_rdata32 <= test_status_reg;
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AMBER_TEST_FIRQ_TIMER: wb_rdata32 <= {24'd0, firq_timer};
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AMBER_TEST_FIRQ_TIMER: wb_rdata32 <= {24'd0, firq_timer};
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AMBER_TEST_IRQ_TIMER: wb_rdata32 <= {24'd0, irq_timer};
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AMBER_TEST_IRQ_TIMER: wb_rdata32 <= {24'd0, irq_timer};
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AMBER_TEST_RANDOM_NUM: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM: wb_rdata32 <= {24'd0, random_num};
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/* Allow access to the random register over
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/* Allow access to the random register over
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a 16-word address range to load a series
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a 16-word address range to load a series
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of random numbers using lmd instruction. */
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of random numbers using lmd instruction. */
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AMBER_TEST_RANDOM_NUM00: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM00: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM01: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM01: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM02: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM02: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM03: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM03: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM04: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM04: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM05: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM05: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM06: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM06: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM07: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM07: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM08: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM08: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM09: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM09: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM10: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM10: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM11: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM11: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM12: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM12: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM13: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM13: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM14: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM14: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM15: wb_rdata32 <= {24'd0, random_num};
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AMBER_TEST_RANDOM_NUM15: wb_rdata32 <= {24'd0, random_num};
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//synopsys translate_off
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//synopsys translate_off
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AMBER_TEST_UART_CONTROL: wb_rdata32 <= {30'd0, tb_uart_control_reg};
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AMBER_TEST_UART_CONTROL: wb_rdata32 <= {30'd0, tb_uart_control_reg};
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AMBER_TEST_UART_STATUS: wb_rdata32 <= {30'd0, tb_uart_status_reg};
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AMBER_TEST_UART_STATUS: wb_rdata32 <= {30'd0, tb_uart_status_reg};
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AMBER_TEST_UART_TXD: wb_rdata32 <= {24'd0, tb_uart_txd_reg};
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AMBER_TEST_UART_TXD: wb_rdata32 <= {24'd0, tb_uart_txd_reg};
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//synopsys translate_on
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//synopsys translate_on
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AMBER_TEST_SIM_CTRL: wb_rdata32 <= {29'd0, sim_ctrl_reg};
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AMBER_TEST_SIM_CTRL: wb_rdata32 <= {29'd0, sim_ctrl_reg};
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AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};
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AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};
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AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;
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AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;
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AMBER_TEST_LED: wb_rdata32 <= {27'd0, led_reg};
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AMBER_TEST_LED: wb_rdata32 <= {27'd0, led_reg};
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AMBER_TEST_PHY_RST: wb_rdata32 <= {31'd0, phy_rst_reg};
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AMBER_TEST_PHY_RST: wb_rdata32 <= {31'd0, phy_rst_reg};
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default: wb_rdata32 <= 32'haabbccdd;
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default: wb_rdata32 <= 32'haabbccdd;
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endcase
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endcase
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// ======================================
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// ======================================
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// Simulation bit
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// Simulation bit
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// ======================================
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// ======================================
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// This register bit is a 1 in simulation but a 0 in the real fpga
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// This register bit is a 1 in simulation but a 0 in the real fpga
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// Used by software to tell the difference
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// Used by software to tell the difference
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//synopsys translate_off
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//synopsys translate_off
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`ifndef AMBER_SIM_CTRL
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`ifndef AMBER_SIM_CTRL
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`define AMBER_SIM_CTRL 0
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`define AMBER_SIM_CTRL 0
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`endif
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`endif
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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// Value reads as 1 in simulation, and zero in the FPGA
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// Value reads as 1 in simulation, and zero in the FPGA
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sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
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sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
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end
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end
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//synopsys translate_on
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//synopsys translate_on
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// ======================================
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// ======================================
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// Interrupts
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// Interrupts
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// ======================================
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// ======================================
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assign o_irq = irq_timer == 8'd1;
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assign o_irq = irq_timer == 8'd1;
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assign o_firq = firq_timer == 8'd1;
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assign o_firq = firq_timer == 8'd1;
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// ======================================
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// ======================================
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// FIRQ Timer Register
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// FIRQ Timer Register
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// ======================================
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// ======================================
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// Write a value > 1 to set the firq timer
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// Write a value > 1 to set the firq timer
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// Write 0 to clear it
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// Write 0 to clear it
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )
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firq_timer <= wb_wdata32[7:0];
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firq_timer <= wb_wdata32[7:0];
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else if ( firq_timer > 8'd1 )
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else if ( firq_timer > 8'd1 )
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firq_timer <= firq_timer - 1'd1;
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firq_timer <= firq_timer - 1'd1;
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|
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|
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// ======================================
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// ======================================
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// IRQ Timer Register
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// IRQ Timer Register
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// ======================================
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// ======================================
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// Write a value > 1 to set the irq timer
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// Write a value > 1 to set the irq timer
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// Write 0 to clear it
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// Write 0 to clear it
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )
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irq_timer <= wb_wdata32[7:0];
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irq_timer <= wb_wdata32[7:0];
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else if ( irq_timer > 8'd1 )
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else if ( irq_timer > 8'd1 )
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irq_timer <= irq_timer - 1'd1;
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irq_timer <= irq_timer - 1'd1;
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|
|
|
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// ======================================
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// ======================================
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// Random Number Generator Register
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// Random Number Generator Register
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// ======================================
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// ======================================
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// Write a value > 1 to set the irq timer
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// Write a value > 1 to set the irq timer
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// Write 0 to clear it
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// Write 0 to clear it
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always @( posedge i_clk )
|
always @( posedge i_clk )
|
begin
|
begin
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if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
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if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
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random_num <= wb_wdata32[7:0];
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random_num <= wb_wdata32[7:0];
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|
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// generate a new random number on every read access
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// generate a new random number on every read access
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else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
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else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
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random_num <= { random_num[3]^random_num[1],
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random_num <= { random_num[3]^random_num[1],
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random_num[0]^random_num[5],
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random_num[0]^random_num[5],
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~random_num[7]^random_num[4],
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~random_num[7]^random_num[4],
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~random_num[2],
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~random_num[2],
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random_num[6],
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random_num[6],
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random_num[4]^~random_num[3],
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random_num[4]^~random_num[3],
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random_num[7]^~random_num[1],
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random_num[7]^~random_num[1],
|
random_num[7]
|
random_num[7]
|
};
|
};
|
end
|
end
|
|
|
|
|
// ======================================
|
// ======================================
|
// Test Status Write
|
// Test Status Write
|
// ======================================
|
// ======================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
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test_status_reg <= wb_wdata32;
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test_status_reg <= wb_wdata32;
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|
|
|
|
// ======================================
|
// ======================================
|
// Test Status Write
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// Test Status Write
|
// ======================================
|
// ======================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
|
test_status_set <= 1'd1;
|
test_status_set <= 1'd1;
|
|
|
|
|
// ======================================
|
// ======================================
|
// Cycles counter
|
// Cycles counter
|
// ======================================
|
// ======================================
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
cycles_reg <= cycles_reg + 1'd1;
|
cycles_reg <= cycles_reg + 1'd1;
|
|
|
|
|
// ======================================
|
// ======================================
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// Memory Configuration Register Write
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// Memory Configuration Register Write
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// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
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mem_ctrl_reg <= wb_wdata32[0];
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mem_ctrl_reg <= wb_wdata32[0];
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|
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// ======================================
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// ======================================
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// Test LEDs
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// Test LEDs
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// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )
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led_reg <= wb_wdata32[3:0];
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led_reg <= wb_wdata32[3:0];
|
|
|
|
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// ======================================
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// ======================================
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// PHY Reset Register
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// PHY Reset Register
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// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )
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if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )
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phy_rst_reg <= wb_wdata32[0];
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phy_rst_reg <= wb_wdata32[0];
|
|
|
|
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// ======================================
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// ======================================
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// Test UART registers
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// Test UART registers
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// ======================================
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// ======================================
|
// These control the testbench UART, not the real
|
// These control the testbench UART, not the real
|
// UART in system
|
// UART in system
|
|
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//synopsys translate_off
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//synopsys translate_off
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always @( posedge i_clk )
|
always @( posedge i_clk )
|
begin
|
begin
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )
|
tb_uart_control_reg <= wb_wdata32[1:0];
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tb_uart_control_reg <= wb_wdata32[1:0];
|
|
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )
|
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )
|
begin
|
begin
|
tb_uart_txd_reg <= wb_wdata32[7:0];
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tb_uart_txd_reg <= wb_wdata32[7:0];
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tb_uart_push <= !tb_uart_push;
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tb_uart_push <= !tb_uart_push;
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end
|
end
|
end
|
end
|
//synopsys translate_on
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//synopsys translate_on
|
|
|
|
|
|
|
endmodule
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endmodule
|
|
|
|
|
