| Line 480... |
Line 480... |
}
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}
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my $ok = def_image_button('icons/select.png','OK');
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my $ok = def_image_button('icons/select.png','OK');
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my $okbox=def_hbox(TRUE,0);
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my $okbox=def_hbox(TRUE,0);
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$okbox->pack_start($ok, FALSE, FALSE,0);
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$okbox->pack_start($ok, FALSE, FALSE,0);
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| Line 823... |
Line 805... |
$type='Spin-button';
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$type='Spin-button';
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$info=($router_type eq '"VC_BASED"')? 'Buffer queue size per VC in flits' : 'Buffer queue size in flits';
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$info=($router_type eq '"VC_BASED"')? 'Buffer queue size per VC in flits' : 'Buffer queue size in flits';
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$row= noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',undef);
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$row= noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',undef);
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#packet payload width
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#packet payload width
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$label='payload width';
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$label='Payload width';
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$param='Fpay';
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$param='Fpay';
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$default='32';
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$default='32';
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$content='32,256,32';
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$content='32,256,32';
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$type='Spin-button';
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$type='Spin-button';
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$info="The packet payload width in bits";
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$info="The packet payload width in bits";
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| Line 1002... |
Line 984... |
$content=1;
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$content=1;
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$default="1\'b0";
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$default="1\'b0";
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$info="If enabeled it adds a pipline register at the output port of the router.";
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$info="If enabeled it adds a pipline register at the output port of the router.";
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$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
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$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
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#MAX_SBP_NUM = 4 //
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$label="Number of multiple router bypassing ";
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$param="MAX_SBP_NUM ";
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$type='Spin-button';
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$content='0,1,1';
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$default=0;
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$info="maximum number of routers which a packet can by pass during one clock cycle. Define it as zero will disable bypassing.";
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#$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
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#FIRST_ARBITER_EXT_P_EN
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#FIRST_ARBITER_EXT_P_EN
|
$label='Swich allocator first level
|
$label='Swich allocator first level
|
arbiters extenal priority enable';
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arbiters external priority enable';
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$param='FIRST_ARBITER_EXT_P_EN';
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$param='FIRST_ARBITER_EXT_P_EN';
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$default= 1;
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$default= 1;
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$info='If set as 1 then the switch allocator\'s input (first) arbiters\' priority registers are enabled only when a request get both input and output arbiters\' grants';
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$info='If set as 1 then the switch allocator\'s input (first) arbiters\' priority registers are enabled only when a request get both input and output arbiters\' grants';
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$content='0,1';
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$content='0,1';
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$type="Combo-box";
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$type="Combo-box";
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$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,$adv_set,'noc_param');
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$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,$adv_set,'noc_param');
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#Arbiter type
|
#Arbiter type
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$label='SW allocator arbiteration type';
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$label='SW allocator arbitration type';
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$param='SWA_ARBITER_TYPE';
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$param='SWA_ARBITER_TYPE';
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$default='"RRA"';
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$default='"RRA"';
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$content='"RRA","WRRA"'; #,"WRRA_CLASSIC"';
|
$content='"RRA","WRRA"'; #,"WRRA_CLASSIC"';
|
$type='Combo-box';
|
$type='Combo-box';
|
$info="Switch allocator arbitertion type:
|
$info="Switch allocator arbitertion type:
|
| Line 1200... |
Line 1193... |
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
|
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
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|
#remove old rtl files that were copied by ProNoC
|
|
my $old_file_ref= eval { do "$hw_dir/file_list" };
|
|
if (defined $old_file_ref){
|
|
remove_file_and_folders($old_file_ref,$target_dir);
|
|
}
|
my @generated_tiles;
|
my @generated_tiles;
|
|
unlink "$hw_dir/file_list";
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|
|
#print "nx=$nx,ny=$ny\n";
|
#print "nx=$nx,ny=$ny\n";
|
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
|
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
|
|
|
my $tile_num= $y*$nx+$x;
|
my $tile_num= $y*$nx+$x;
|
#print "$tile_num\n";
|
#print "$tile_num\n";
|
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
|
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
|
|
next if(!defined $soc_name);
|
|
|
|
|
my $path=$mpsoc->object_get_attribute('setting','soc_path');
|
my $path=$mpsoc->object_get_attribute('setting','soc_path');
|
$path=~ s/ /\\ /g;
|
$path=~ s/ /\\ /g;
|
my $p = "$path/$soc_name.SOC";
|
my $p = "$path/$soc_name.SOC";
|
my $soc = eval { do $p };
|
my $soc = eval { do $p };
|
if ($@ || !defined $soc){
|
if ($@ || !defined $soc){
|
| Line 1239... |
Line 1239... |
if( grep (/^$soc_name$/,@generated_tiles)){ # This soc is generated before only create the software file
|
if( grep (/^$soc_name$/,@generated_tiles)){ # This soc is generated before only create the software file
|
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,0);
|
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,0);
|
}else{
|
}else{
|
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1);
|
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1);
|
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
|
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
|
|
my @tmp= ("$hw_dir/tiles/$soc_name.v");
|
|
add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir);
|
|
|
}
|
}
|
|
|
|
|
}}
|
}}
|
| Line 1302... |
Line 1304... |
|
|
|
|
}
|
}
|
show_info(\$info,$warnings) if(defined $warnings);
|
show_info(\$info,$warnings) if(defined $warnings);
|
|
|
|
#save project hdl file/folder list
|
|
my @new_file_ref;
|
|
foreach my $f(@{$hdl_ref}){
|
|
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
|
|
push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix");
|
|
}
|
|
open(FILE, ">$target_dir/src_verilog/file_list") || die "Can not open: $!";
|
|
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
|
|
close(FILE) || die "Error closing file: $!";
|
|
|
#my @pathes=("$dir/../src_peripheral","$dir/../src_noc","$dir/../src_processor");
|
#my @pathes=("$dir/../src_peripheral","$dir/../src_noc","$dir/../src_processor");
|
#foreach my $p(@pathes){
|
#foreach my $p(@pathes){
|
# find(
|
# find(
|
# sub {
|
# sub {
|
| Line 1357... |
Line 1368... |
################
|
################
|
# generate_mpsoc
|
# generate_mpsoc
|
#################
|
#################
|
|
|
sub generate_mpsoc{
|
sub generate_mpsoc{
|
my ($mpsoc,$info)=@_;
|
my ($mpsoc,$info,$show_sucess_msg)=@_;
|
my $name=$mpsoc->object_get_attribute('mpsoc_name');
|
my $name=$mpsoc->object_get_attribute('mpsoc_name');
|
my $error = check_verilog_identifier_syntax($name);
|
my $error = check_verilog_identifier_syntax($name);
|
if ( defined $error ){
|
if ( defined $error ){
|
message_dialog("The \"$name\" is given with an unacceptable formatting. The mpsoc name will be used as top level verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
|
message_dialog("The \"$name\" is given with an unacceptable formatting. The mpsoc name will be used as top level verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
|
return 0;
|
return 0;
|
| Line 1428... |
Line 1439... |
close(FILE) || die "Error closing file: $!";
|
close(FILE) || die "Error closing file: $!";
|
|
|
|
|
|
|
|
|
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
|
message_dialog("MPSoC \"$name\" has been created successfully at $target_dir/ " ) if($show_sucess_msg);
|
|
|
|
|
|
|
return 1;
|
return 1;
|
}
|
}
|
| Line 1480... |
Line 1491... |
|
|
|
|
|
|
#programe the memory
|
#programe the memory
|
for i in $(ls -d */); do
|
for i in $(ls -d */); do
|
|
echo "Enter ${i%%/}"
|
cd ${i%%/}
|
cd ${i%%/}
|
sh write_memory.sh
|
sh write_memory.sh
|
cd ..
|
cd ..
|
done
|
done
|
|
|
| Line 1633... |
Line 1645... |
|
|
my @socs=$mpsoc->mpsoc_get_soc_list();
|
my @socs=$mpsoc->mpsoc_get_soc_list();
|
my @list=(' ',@socs);
|
my @list=(' ',@socs);
|
my $pos=(defined $soc_name)? get_scolar_pos($soc_name,@list): 0;
|
my $pos=(defined $soc_name)? get_scolar_pos($soc_name,@list): 0;
|
my $combo=gen_combo(\@list, $pos);
|
my $combo=gen_combo(\@list, $pos);
|
my $lable=gen_label_in_left(" SoC name:");
|
my $lable=gen_label_in_left(" Processing tile name:");
|
$table->attach_defaults($lable,0,3,$row,$row+1);
|
$table->attach_defaults($lable,0,3,$row,$row+1);
|
$table->attach_defaults($combo,3,7,$row,$row+1);$row++;
|
$table->attach_defaults($combo,3,7,$row,$row+1);$row++;
|
my $separator1 = Gtk2::HSeparator->new;
|
my $separator1 = Gtk2::HSeparator->new;
|
$table->attach_defaults($separator1,0,7,$row,$row+1);$row++;
|
$table->attach_defaults($separator1,0,7,$row,$row+1);$row++;
|
|
|
| Line 1765... |
Line 1777... |
my $name=$self->object_get_attribute('mpsoc_name');
|
my $name=$self->object_get_attribute('mpsoc_name');
|
if (length($name)==0){
|
if (length($name)==0){
|
message_dialog("Please define the MPSoC name!");
|
message_dialog("Please define the MPSoC name!");
|
return ;
|
return ;
|
}
|
}
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name/sw";
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
|
my $sw = "$target_dir";
|
my $sw = "$target_dir/sw";
|
my ($app,$table,$tview) = software_main($sw);
|
my ($app,$table,$tview) = software_main($sw);
|
|
|
|
|
|
|
|
|
my $make = def_image_button('icons/gen.png','Compile');
|
my $make = def_image_button('icons/gen.png','Compile');
|
|
my $prog= def_image_button('icons/write.png','Program the memories');
|
|
|
|
|
$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
|
|
|
$table->attach ($make,5, 6, 1,2,'shrink','shrink',0,0);
|
|
$table->attach ($prog,9, 10, 1,2,'shrink','shrink',0,0);
|
|
|
|
|
$make -> signal_connect("clicked" => sub{
|
$make -> signal_connect("clicked" => sub{
|
$app->do_save();
|
$app->do_save();
|
append_to_textview($tview,' ');
|
append_to_textview($tview,' ');
|
run_make_file($sw,$tview);
|
run_make_file($sw,$tview);
|
|
|
});
|
});
|
|
|
|
#Programe the board
|
|
$prog-> signal_connect("clicked" => sub{
|
|
my $error = 0;
|
|
my $bash_file="$sw/program.sh";
|
|
my $jtag_intfc="$sw/jtag_intfc.sh";
|
|
|
|
add_info(\$tview,"Programe the board using quartus_pgm and $bash_file file\n");
|
|
#check if the programming file exists
|
|
unless (-f $bash_file) {
|
|
add_colored_info(\$tview,"\tThe $bash_file does not exists! \n", 'red');
|
|
$error=1;
|
|
}
|
|
#check if the jtag_intfc.sh file exists
|
|
unless (-f $jtag_intfc) {
|
|
add_colored_info(\$tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
|
|
$error=1;
|
|
}
|
|
|
|
return if($error);
|
|
my $command = "cd $sw; sh program.sh";
|
|
add_info(\$tview,"$command\n");
|
|
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
|
|
if(length $stderr>1){
|
|
add_colored_info(\$tview,"$stderr\n",'red');
|
|
add_colored_info(\$tview,"Memory was not programed successfully!\n",'red');
|
|
}else {
|
|
|
|
if($exit){
|
|
add_colored_info(\$tview,"$stdout\n",'red');
|
|
add_colored_info(\$tview,"Memory was not programed successfully!\n",'red');
|
|
}else{
|
|
add_info(\$tview,"$stdout\n");
|
|
add_colored_info(\$tview,"Memory is programed successfully!\n",'blue');
|
|
|
|
}
|
|
|
|
}
|
|
});
|
|
|
}
|
}
|
|
|
|
|
|
|
#############
|
#############
|
| Line 1944... |
Line 1998... |
|
|
} );
|
} );
|
|
|
|
|
$generate-> signal_connect("clicked" => sub{
|
$generate-> signal_connect("clicked" => sub{
|
generate_mpsoc($mpsoc,$info);
|
generate_mpsoc($mpsoc,$info,1);
|
set_gui_status($mpsoc,"refresh_soc",1);
|
set_gui_status($mpsoc,"refresh_soc",1);
|
|
|
});
|
});
|
|
|
|
|
| Line 1967... |
Line 2021... |
return ;
|
return ;
|
}
|
}
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
|
my $top_file = "$target_dir/src_verilog/${name}_top.v";
|
my $top_file = "$target_dir/src_verilog/${name}_top.v";
|
if (-f $top_file){
|
if (-f $top_file){
|
|
generate_mpsoc($mpsoc,$info,0);
|
select_compiler($mpsoc,$name,$top_file,$target_dir);
|
select_compiler($mpsoc,$name,$top_file,$target_dir);
|
} else {
|
} else {
|
message_dialog("Cannot find $top_file file. Please run RTL Generator first!");
|
message_dialog("Cannot find $top_file file. Please run RTL Generator first!");
|
return;
|
return;
|
}
|
}
|
