URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Show entire file |
Details |
Blame |
View Log
Rev 48 |
Rev 56 |
Line 754... |
Line 754... |
print FILE perl_file_header("$name.SOC");
|
print FILE perl_file_header("$name.SOC");
|
print FILE Data::Dumper->Dump([\%$soc],['soc']);
|
print FILE Data::Dumper->Dump([\%$soc],['soc']);
|
close(FILE) || die "Error closing file: $!";
|
close(FILE) || die "Error closing file: $!";
|
|
|
# Write verilog file
|
# Write verilog file
|
my $h=autogen_warning().get_license_header("${name}.sv")."\n`timescale 1ns / 1ps\n";
|
my $h=autogen_warning().get_license_header("${name}.sv")."\n";
|
open(FILE, ">lib/verilog/$name.sv") || die "Can not open: $!";
|
open(FILE, ">lib/verilog/$name.sv") || die "Can not open: $!";
|
print FILE $h.$file_v;
|
print FILE $h.$file_v;
|
close(FILE) || die "Error closing file: $!";
|
close(FILE) || die "Error closing file: $!";
|
|
|
# Write Top module file
|
# Write Top module file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.