`include "pronoc_def.v"
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`include "pronoc_def.v"
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//`define MONITORE_PATH
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//`define MONITORE_PATH
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/**********************************************************************
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/**********************************************************************
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** File: input_ports.sv
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** File: input_ports.sv
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see .
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** License along with ProNoC. If not, see .
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**
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**
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**
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**
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** Description:
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** Description:
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** NoC router input Port. It consists of input buffer, control FIFO
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** NoC router input Port. It consists of input buffer, control FIFO
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** and request masking/generation control modules
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** and request masking/generation control modules
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**
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**
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**************************************************************/
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**************************************************************/
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module input_ports #(
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parameter NOC_ID=0,
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module input_ports
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import pronoc_pkg::*;
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#(
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parameter P=5
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parameter P=5
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)(
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) (
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current_r_addr,
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current_r_addr,
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neighbors_r_addr,
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neighbors_r_addr,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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any_ivc_sw_request_granted_all,
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any_ivc_sw_request_granted_all,
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flit_in_all,
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flit_in_all,
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flit_in_wr_all,
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flit_in_wr_all,
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reset_ivc_all,
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reset_ivc_all,
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flit_is_tail_all,
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flit_is_tail_all,
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ivc_request_all,
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ivc_request_all,
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dest_port_all,
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dest_port_all,
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flit_out_all,
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flit_out_all,
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assigned_ovc_not_full_all,
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assigned_ovc_not_full_all,
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ovc_is_assigned_all,
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ovc_is_assigned_all,
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sel,
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sel,
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port_pre_sel,
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port_pre_sel,
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swap_port_presel,
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swap_port_presel,
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nonspec_first_arbiter_granted_ivc_all,
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nonspec_first_arbiter_granted_ivc_all,
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credit_out_all,
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credit_out_all,
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destport_clear,
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destport_clear,
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vc_weight_is_consumed_all,
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vc_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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iport_weight_all,
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iport_weight_all,
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oports_weight_all,
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oports_weight_all,
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granted_dest_port_all,
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granted_dest_port_all,
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refresh_w_counter,
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refresh_w_counter,
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ivc_info,
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ivc_info,
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vsa_ctrl_in,
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vsa_ctrl_in,
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ssa_ctrl_in,
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ssa_ctrl_in,
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smart_ctrl_in,
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smart_ctrl_in,
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credit_init_val_out,
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credit_init_val_out,
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reset,
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reset,
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clk
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clk
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);
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);
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`NOC_CONF
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localparam
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localparam
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PV = V * P,
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PV = V * P,
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VV = V * V,
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VV = V * V,
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PVV = PV * V,
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PVV = PV * V,
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P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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PP_1 = P * P_1,
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PP_1 = P * P_1,
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VP_1 = V * P_1,
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VP_1 = V * P_1,
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PVP_1 = PV * P_1,
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PVP_1 = PV * P_1,
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PFw = P*Fw,
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PFw = P*Fw,
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W= WEIGHTw,
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W= WEIGHTw,
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WP= W * P,
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WP= W * P,
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WPP = WP * P,
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WPP = WP * P,
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PVDSTPw= PV * DSTPw,
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PVDSTPw= PV * DSTPw,
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PRAw= P * RAw;
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PRAw= P * RAw;
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input reset,clk;
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input reset,clk;
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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output [PV-1 : 0] ivc_num_getting_sw_grant;
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output [PV-1 : 0] ivc_num_getting_sw_grant;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [PFw-1 : 0] flit_in_all;
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input [PFw-1 : 0] flit_in_all;
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input [P-1 : 0] flit_in_wr_all;
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input [P-1 : 0] flit_in_wr_all;
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output [PV-1 : 0] reset_ivc_all;
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output [PV-1 : 0] reset_ivc_all;
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output [PV-1 : 0] flit_is_tail_all;
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output [PV-1 : 0] flit_is_tail_all;
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output [PV-1 : 0] ivc_request_all;
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output [PV-1 : 0] ivc_request_all;
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output [PV-1 : 0] credit_out_all;
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output [PV-1 : 0] credit_out_all;
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output [PVP_1-1 : 0] dest_port_all;
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output [PVP_1-1 : 0] dest_port_all;
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output [PFw-1 : 0] flit_out_all;
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output [PFw-1 : 0] flit_out_all;
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input [PV-1 : 0] assigned_ovc_not_full_all;
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input [PV-1 : 0] assigned_ovc_not_full_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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input [PV-1 : 0] sel;
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input [PV-1 : 0] sel;
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input [PPSw-1 : 0] port_pre_sel;
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input [PPSw-1 : 0] port_pre_sel;
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input [PV-1 : 0] swap_port_presel;
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input [PV-1 : 0] swap_port_presel;
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input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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output [WP-1 : 0] iport_weight_all;
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output [WP-1 : 0] iport_weight_all;
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output [PV-1 : 0] vc_weight_is_consumed_all;
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output [PV-1 : 0] vc_weight_is_consumed_all;
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output [P-1 : 0] iport_weight_is_consumed_all;
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output [P-1 : 0] iport_weight_is_consumed_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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output [WPP-1 : 0] oports_weight_all;
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output [WPP-1 : 0] oports_weight_all;
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output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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input refresh_w_counter;
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input refresh_w_counter;
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input [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
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input [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
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genvar i;
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genvar i;
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generate
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generate
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for(i=0;i
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for(i=0;i
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input_queue_per_port
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input_queue_per_port
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// iport_reg_base
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// iport_reg_base
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#(
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#(
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.NOC_ID(NOC_ID),
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.SW_LOC(i),
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.SW_LOC(i),
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.P(P)
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.P(P)
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)
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) the_input_queue_per_port (
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the_input_queue_per_port
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(
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.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
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.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.neighbors_r_addr(neighbors_r_addr),
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.neighbors_r_addr(neighbors_r_addr),
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.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
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.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
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.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
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.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all [i]),
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.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
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.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
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.flit_in_wr(flit_in_wr_all[i]),
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.flit_in_wr(flit_in_wr_all[i]),
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.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
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.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
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.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
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.flit_is_tail(flit_is_tail_all [(i+1)*V-1 : i*V]),
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.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
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.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),
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.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
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.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
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.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
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.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
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.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
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.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]),
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.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
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.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]),
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.sel(sel [(i+1)*V-1 : i*V]),
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.sel(sel [(i+1)*V-1 : i*V]),
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.port_pre_sel(port_pre_sel),
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.port_pre_sel(port_pre_sel),
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.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
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.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
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.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
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.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.destport_clear(destport_clear [i]),
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.destport_clear(destport_clear [i]),
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.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
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.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
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.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
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.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
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.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
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.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
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.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
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.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
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.refresh_w_counter(refresh_w_counter),
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.refresh_w_counter(refresh_w_counter),
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.granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
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.granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
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.ivc_info(ivc_info[i]),
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.ivc_info(ivc_info[i]),
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.vsa_ctrl_in(vsa_ctrl_in [i]),
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.vsa_ctrl_in(vsa_ctrl_in [i]),
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.smart_ctrl_in(smart_ctrl_in [i]),
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.smart_ctrl_in(smart_ctrl_in [i]),
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.ssa_ctrl_in(ssa_ctrl_in [i]),
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.ssa_ctrl_in(ssa_ctrl_in [i]),
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.credit_init_val_out(credit_init_val_out[i])
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.credit_init_val_out(credit_init_val_out[i])
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);
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);
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end//for
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end//for
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endgenerate
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endgenerate
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endmodule
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endmodule
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/**************************
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/**************************
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input_queue_per_port
|
input_queue_per_port
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**************************/
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**************************/
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module input_queue_per_port
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module input_queue_per_port #(
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import pronoc_pkg::*;
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parameter NOC_ID=0,
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#(
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parameter P = 5, // router port num
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parameter P = 5, // router port num
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parameter SW_LOC = 0
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parameter SW_LOC = 0
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)(
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) (
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current_r_addr,
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current_r_addr,
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credit_out,
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credit_out,
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neighbors_r_addr,
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neighbors_r_addr,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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any_ivc_sw_request_granted,
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any_ivc_sw_request_granted,
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flit_in,
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flit_in,
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flit_in_wr,
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flit_in_wr,
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reset_ivc,
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reset_ivc,
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flit_is_tail,
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flit_is_tail,
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ivc_request,
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ivc_request,
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dest_port,
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dest_port,
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flit_out,
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flit_out,
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assigned_ovc_not_full,
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assigned_ovc_not_full,
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ovc_is_assigned,
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ovc_is_assigned,
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sel,
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sel,
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port_pre_sel,
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port_pre_sel,
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swap_port_presel,
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swap_port_presel,
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reset,
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reset,
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clk,
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clk,
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nonspec_first_arbiter_granted_ivc,
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nonspec_first_arbiter_granted_ivc,
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destport_clear,
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destport_clear,
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|
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iport_weight,
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iport_weight,
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oports_weight,
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oports_weight,
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vc_weight_is_consumed,
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vc_weight_is_consumed,
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iport_weight_is_consumed,
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iport_weight_is_consumed,
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refresh_w_counter,
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refresh_w_counter,
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granted_dest_port,
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granted_dest_port,
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ivc_info,
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ivc_info,
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smart_ctrl_in,
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smart_ctrl_in,
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vsa_ctrl_in,
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vsa_ctrl_in,
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ssa_ctrl_in,
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ssa_ctrl_in,
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credit_init_val_out
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credit_init_val_out
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);
|
);
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|
|
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`NOC_CONF
|
|
|
|
|
|
|
localparam
|
localparam
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PORT_B = port_buffer_size(SW_LOC),
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PORT_B = port_buffer_size(SW_LOC),
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PORT_Bw= log2(PORT_B);
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PORT_Bw= log2(PORT_B);
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|
|
|
|
|
|
localparam
|
localparam
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VV = V * V,
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VV = V * V,
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VDSTPw = V * DSTPw,
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VDSTPw = V * DSTPw,
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W = WEIGHTw,
|
W = WEIGHTw,
|
WP = W * P,
|
WP = W * P,
|
P_1=( SELF_LOOP_EN=="NO")? P-1 : P,
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P_1=( SELF_LOOP_EN=="NO")? P-1 : P,
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VP_1 = V * P_1;
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VP_1 = V * P_1;
|
|
|
localparam
|
localparam
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
OFFSET = (PORT_B%MIN_PCK_SIZE)? 1 :0,
|
OFFSET = (PORT_B%MIN_PCK_SIZE)? 1 :0,
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NON_ATOM_PCKS = (PORT_B>MIN_PCK_SIZE)? (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
|
NON_ATOM_PCKS = (PORT_B>MIN_PCK_SIZE)? (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
|
MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")? 1 : NON_ATOM_PCKS + OVC_ALLOC_MODE,// min packet size is two hence the max packet number in buffer is (B/2)
|
MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")? 1 : NON_ATOM_PCKS + OVC_ALLOC_MODE,// min packet size is two hence the max packet number in buffer is (B/2)
|
IGNORE_SAME_LOC_RD_WR_WARNING = ((SSA_EN=="YES")| SMART_EN)? "YES" : "NO";
|
IGNORE_SAME_LOC_RD_WR_WARNING = ((SSA_EN=="YES")| SMART_EN)? "YES" : "NO";
|
|
|
|
|
localparam
|
localparam
|
ELw = log2(T3),
|
ELw = log2(T3),
|
Pw = log2(P),
|
Pw = log2(P),
|
PLw = (TOPOLOGY == "FMESH") ? Pw : ELw,
|
PLw = (TOPOLOGY == "FMESH") ? Pw : ELw,
|
VPLw= V * PLw,
|
VPLw= V * PLw,
|
PRAw= P * RAw;
|
PRAw= P * RAw;
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
input reset, clk;
|
input reset, clk;
|
output [V-1 : 0] credit_out;
|
output [V-1 : 0] credit_out;
|
input [RAw-1 : 0] current_r_addr;
|
input [RAw-1 : 0] current_r_addr;
|
input [PRAw-1: 0] neighbors_r_addr;
|
input [PRAw-1: 0] neighbors_r_addr;
|
output [V-1 : 0] ivc_num_getting_sw_grant;
|
output [V-1 : 0] ivc_num_getting_sw_grant;
|
input any_ivc_sw_request_granted;
|
input any_ivc_sw_request_granted;
|
input [Fw-1 : 0] flit_in;
|
input [Fw-1 : 0] flit_in;
|
input flit_in_wr;
|
input flit_in_wr;
|
output [V-1 : 0] reset_ivc;
|
output [V-1 : 0] reset_ivc;
|
output [V-1 : 0] flit_is_tail;
|
output [V-1 : 0] flit_is_tail;
|
output [V-1 : 0] ivc_request;
|
output [V-1 : 0] ivc_request;
|
output [VP_1-1 : 0] dest_port;
|
output [VP_1-1 : 0] dest_port;
|
output [Fw-1 : 0] flit_out;
|
output [Fw-1 : 0] flit_out;
|
input [V-1 : 0] assigned_ovc_not_full;
|
input [V-1 : 0] assigned_ovc_not_full;
|
output [V-1 : 0] ovc_is_assigned;
|
output [V-1 : 0] ovc_is_assigned;
|
input [V-1 : 0] sel;
|
input [V-1 : 0] sel;
|
input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
|
input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
|
|
|
input [DSTPw-1 : 0] destport_clear [V-1 : 0];
|
input [DSTPw-1 : 0] destport_clear [V-1 : 0];
|
output [WEIGHTw-1 : 0] iport_weight;
|
output [WEIGHTw-1 : 0] iport_weight;
|
output [V-1 : 0] vc_weight_is_consumed;
|
output [V-1 : 0] vc_weight_is_consumed;
|
output iport_weight_is_consumed;
|
output iport_weight_is_consumed;
|
input refresh_w_counter;
|
input refresh_w_counter;
|
input [P_1-1 : 0] granted_dest_port;
|
input [P_1-1 : 0] granted_dest_port;
|
output [WP-1 : 0] oports_weight;
|
output [WP-1 : 0] oports_weight;
|
input [PPSw-1 : 0] port_pre_sel;
|
input [PPSw-1 : 0] port_pre_sel;
|
input [V-1 : 0] swap_port_presel;
|
input [V-1 : 0] swap_port_presel;
|
|
|
output ivc_info_t ivc_info [V-1 : 0];
|
output ivc_info_t ivc_info [V-1 : 0];
|
input smart_ctrl_t smart_ctrl_in;
|
input smart_ctrl_t smart_ctrl_in;
|
input vsa_ctrl_t vsa_ctrl_in;
|
input vsa_ctrl_t vsa_ctrl_in;
|
input ssa_ctrl_t ssa_ctrl_in;
|
input ssa_ctrl_t ssa_ctrl_in;
|
output [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
|
output [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
|
|
|
wire [DSTPw-1 : 0] dest_port_encoded [V-1 : 0];
|
wire [DSTPw-1 : 0] dest_port_encoded [V-1 : 0];
|
//for multicast
|
//for multicast
|
wire [DSTPw-1 : 0] dest_port_multi [V-1 : 0];
|
wire [DSTPw-1 : 0] dest_port_multi [V-1 : 0];
|
wire [V-1 : 0] multiple_dest,dst_onhot0;
|
wire [V-1 : 0] multiple_dest,dst_onhot0;
|
wire [DSTPw-1 : 0] clear_dspt_mulicast [V-1 : 0];
|
wire [DSTPw-1 : 0] clear_dspt_mulicast [V-1 : 0];
|
|
|
wire [VV-1 : 0] candidate_ovcs;
|
wire [VV-1 : 0] candidate_ovcs;
|
|
|
wire [Cw-1 : 0] class_in;
|
wire [Cw-1 : 0] class_in;
|
wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
|
wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
|
wire [VDSTPw-1 : 0] lk_destination_encoded;
|
wire [VDSTPw-1 : 0] lk_destination_encoded;
|
|
|
wire [DAw-1 : 0] dest_e_addr_in;
|
wire [DAw-1 : 0] dest_e_addr_in;
|
wire [EAw-1 : 0] src_e_addr_in;
|
wire [EAw-1 : 0] src_e_addr_in;
|
wire [V-1 : 0] vc_num_in;
|
wire [V-1 : 0] vc_num_in;
|
wire [V-1 : 0] hdr_flit_wr,flit_wr;
|
wire [V-1 : 0] hdr_flit_wr,flit_wr;
|
wire [VV-1 : 0] assigned_ovc_num;
|
wire [VV-1 : 0] assigned_ovc_num;
|
|
|
wire [DSTPw-1 : 0] lk_destination_in_encoded;
|
wire [DSTPw-1 : 0] lk_destination_in_encoded;
|
wire [WEIGHTw-1 : 0] weight_in;
|
wire [WEIGHTw-1 : 0] weight_in;
|
wire [Fw-1 : 0] buffer_out;
|
wire [Fw-1 : 0] buffer_out;
|
wire hdr_flg_in,tail_flg_in;
|
wire hdr_flg_in,tail_flg_in;
|
wire [V-1 : 0] ivc_not_empty;
|
wire [V-1 : 0] ivc_not_empty;
|
wire [Cw-1 : 0] class_out [V-1 : 0];
|
wire [Cw-1 : 0] class_out [V-1 : 0];
|
wire [VPLw-1 : 0] endp_localp_num;
|
wire [VPLw-1 : 0] endp_localp_num;
|
|
|
wire [V-1 : 0] smart_hdr_en;
|
wire [V-1 : 0] smart_hdr_en;
|
wire [ELw-1 : 0] endp_l_in;
|
wire [ELw-1 : 0] endp_l_in;
|
wire [Pw-1 : 0] endp_p_in;
|
wire [Pw-1 : 0] endp_p_in;
|
|
|
wire [V-1 : 0] rd_hdr_fwft_fifo,wr_hdr_fwft_fifo,rd_hdr_fwft_fifo_delay,wr_hdr_fwft_fifo_delay;
|
wire [V-1 : 0] rd_hdr_fwft_fifo,wr_hdr_fwft_fifo,rd_hdr_fwft_fifo_delay,wr_hdr_fwft_fifo_delay;
|
|
|
logic [V-1 : 0] ovc_is_assigned_next;
|
logic [V-1 : 0] ovc_is_assigned_next;
|
logic [VV-1 : 0] assigned_ovc_num_next;
|
logic [VV-1 : 0] assigned_ovc_num_next;
|
|
|
wire odd_column = current_r_addr[0];
|
wire odd_column = current_r_addr[0];
|
wire [P-1 : 0] destport_one_hot [V-1 :0];
|
wire [P-1 : 0] destport_one_hot [V-1 :0];
|
wire [V-1 : 0] mux_out[V-1 : 0];
|
wire [V-1 : 0] mux_out[V-1 : 0];
|
|
|
wire [V-1 : 0] dstport_fifo_not_empty;
|
wire [V-1 : 0] dstport_fifo_not_empty;
|
|
|
logic [WEIGHTw-1 : 0] iport_weight_next;
|
logic [WEIGHTw-1 : 0] iport_weight_next;
|
|
|
assign smart_hdr_en = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
|
assign smart_hdr_en = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
|
assign reset_ivc = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
|
assign reset_ivc = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
|
assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
|
assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
|
assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
|
assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
|
assign rd_hdr_fwft_fifo = (ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset & ~ smart_ctrl_in.ivc_single_flit_pck)) & ~ multiple_dest;
|
assign rd_hdr_fwft_fifo = (ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset & ~ smart_ctrl_in.ivc_single_flit_pck)) & ~ multiple_dest;
|
assign wr_hdr_fwft_fifo = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
|
assign wr_hdr_fwft_fifo = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
|
assign ivc_request = ivc_not_empty;
|
assign ivc_request = ivc_not_empty;
|
|
|
|
|
wire [V-1 : 0] flit_is_tail2;
|
wire [V-1 : 0] flit_is_tail2;
|
|
|
|
|
pronoc_register #(.W(V)) reg1(
|
pronoc_register #(.W(V)) reg1(
|
.in (ovc_is_assigned_next),
|
.in (ovc_is_assigned_next),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (ovc_is_assigned ));
|
.out (ovc_is_assigned ));
|
|
|
pronoc_register #(.W(VV)) reg2(
|
pronoc_register #(.W(VV)) reg2(
|
.in (assigned_ovc_num_next),
|
.in (assigned_ovc_num_next),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (assigned_ovc_num ));
|
.out (assigned_ovc_num ));
|
|
|
pronoc_register #(.W(V)) reg3(
|
pronoc_register #(.W(V)) reg3(
|
.in (rd_hdr_fwft_fifo),
|
.in (rd_hdr_fwft_fifo),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (rd_hdr_fwft_fifo_delay ));
|
.out (rd_hdr_fwft_fifo_delay ));
|
|
|
pronoc_register #(.W(V)) reg4(
|
pronoc_register #(.W(V)) reg4(
|
.in (wr_hdr_fwft_fifo),
|
.in (wr_hdr_fwft_fifo),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (wr_hdr_fwft_fifo_delay ));
|
.out (wr_hdr_fwft_fifo_delay ));
|
|
|
pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
|
pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
|
.in (iport_weight_next ),
|
.in (iport_weight_next ),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (iport_weight ));
|
.out (iport_weight ));
|
|
|
|
|
pronoc_register #(.W(V)) credit_reg (
|
pronoc_register #(.W(V)) credit_reg (
|
.in (ivc_num_getting_sw_grant & ~ multiple_dest),
|
.in (ivc_num_getting_sw_grant & ~ multiple_dest),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk),
|
.clk (clk),
|
.out (credit_out));
|
.out (credit_out));
|
|
|
|
|
|
|
|
|
always @ (*)begin
|
always @ (*)begin
|
iport_weight_next = iport_weight;
|
iport_weight_next = iport_weight;
|
if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
|
if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
|
end
|
end
|
|
|
|
|
//extract header flit info
|
//extract header flit info
|
extract_header_flit_info #(
|
extract_header_flit_info #(
|
|
.NOC_ID(NOC_ID),
|
.DATA_w(0)
|
.DATA_w(0)
|
)
|
) header_extractor (
|
header_extractor
|
|
(
|
|
.flit_in(flit_in),
|
.flit_in(flit_in),
|
.flit_in_wr(flit_in_wr),
|
.flit_in_wr(flit_in_wr),
|
.class_o(class_in),
|
.class_o(class_in),
|
.destport_o(destport_in),
|
.destport_o(destport_in),
|
.dest_e_addr_o(dest_e_addr_in),
|
.dest_e_addr_o(dest_e_addr_in),
|
.src_e_addr_o(src_e_addr_in),
|
.src_e_addr_o(src_e_addr_in),
|
.vc_num_o(vc_num_in),
|
.vc_num_o(vc_num_in),
|
.hdr_flit_wr_o(hdr_flit_wr),
|
.hdr_flit_wr_o(hdr_flit_wr),
|
.hdr_flg_o(hdr_flg_in),
|
.hdr_flg_o(hdr_flg_in),
|
.tail_flg_o(tail_flg_in),
|
.tail_flg_o(tail_flg_in),
|
.weight_o(weight_in),
|
.weight_o(weight_in),
|
.be_o( ),
|
.be_o( ),
|
.data_o( )
|
.data_o( )
|
);
|
);
|
|
|
|
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
|
|
mesh_tori_endp_addr_decode #(
|
mesh_tori_endp_addr_decode #(
|
.TOPOLOGY("MESH"),
|
.TOPOLOGY(TOPOLOGY),
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
|
endp_addr_decode
|
endp_addr_decode
|
(
|
(
|
.e_addr(dest_e_addr_in),
|
.e_addr(dest_e_addr_in),
|
.ex( ),
|
.ex( ),
|
.ey( ),
|
.ey( ),
|
.el(endp_l_in),
|
.el(endp_l_in),
|
.valid( )
|
.valid( )
|
);
|
);
|
end
|
end
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST" ) begin : fmesh
|
if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST" ) begin : fmesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
|
|
fmesh_endp_addr_decode #(
|
fmesh_endp_addr_decode #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
|
endp_addr_decode
|
endp_addr_decode
|
(
|
(
|
.e_addr(dest_e_addr_in),
|
.e_addr(dest_e_addr_in),
|
.ex(),
|
.ex(),
|
.ey(),
|
.ey(),
|
.ep(endp_p_in),
|
.ep(endp_p_in),
|
.valid()
|
.valid()
|
);
|
);
|
|
|
end
|
end
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
|
if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
fattree_destport_up_select #(
|
fattree_destport_up_select #(
|
.K(T1),
|
.K(T1),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC)
|
)
|
)
|
static_sel
|
static_sel
|
(
|
(
|
.destport_in(destport_in),
|
.destport_in(destport_in),
|
.destport_o(destport_in_encoded)
|
.destport_o(destport_in_encoded)
|
);
|
);
|
|
|
end else begin : other
|
end else begin : other
|
assign destport_in_encoded = destport_in;
|
assign destport_in_encoded = destport_in;
|
end
|
end
|
|
|
|
|
for (i=0;i
|
for (i=0;i
|
|
|
assign credit_init_val_out [i] = PORT_B [CRDTw-1 : 0 ];
|
assign credit_init_val_out [i] = PORT_B [CRDTw-1 : 0 ];
|
|
|
|
|
one_hot_to_bin #(.ONE_HOT_WIDTH(V),.BIN_WIDTH(Vw)) conv (
|
one_hot_to_bin #(.ONE_HOT_WIDTH(V),.BIN_WIDTH(Vw)) conv (
|
.one_hot_code(assigned_ovc_num[(i+1)*V-1 : i*V]),
|
.one_hot_code(assigned_ovc_num[(i+1)*V-1 : i*V]),
|
.bin_code(ivc_info[i].assigned_ovc_bin)
|
.bin_code(ivc_info[i].assigned_ovc_bin)
|
);
|
);
|
|
|
assign ivc_info[i].single_flit_pck =
|
assign ivc_info[i].single_flit_pck =
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
(PCK_TYPE == "SINGLE_FLIT")? 1'b1 :
|
(PCK_TYPE == "SINGLE_FLIT")? 1'b1 :
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
(MIN_PCK_SIZE == 1)? flit_is_tail[i] & ~ovc_is_assigned[i] : 1'b0;
|
(MIN_PCK_SIZE == 1)? flit_is_tail[i] & ~ovc_is_assigned[i] : 1'b0;
|
assign ivc_info[i].ivc_req = ivc_request[i];
|
assign ivc_info[i].ivc_req = ivc_request[i];
|
assign ivc_info[i].class_num = class_out[i];
|
assign ivc_info[i].class_num = class_out[i];
|
assign ivc_info[i].flit_is_tail = flit_is_tail[i];
|
assign ivc_info[i].flit_is_tail = flit_is_tail[i];
|
assign ivc_info[i].assigned_ovc_not_full=assigned_ovc_not_full[i];
|
assign ivc_info[i].assigned_ovc_not_full=assigned_ovc_not_full[i];
|
assign ivc_info[i].candidate_ovc= candidate_ovcs [(i+1)*V-1 : i*V];
|
assign ivc_info[i].candidate_ovc= candidate_ovcs [(i+1)*V-1 : i*V];
|
assign ivc_info[i].ovc_is_assigned = ovc_is_assigned[i];
|
assign ivc_info[i].ovc_is_assigned = ovc_is_assigned[i];
|
assign ivc_info[i].assigned_ovc_num= assigned_ovc_num[(i+1)*V-1 : i*V];
|
assign ivc_info[i].assigned_ovc_num= assigned_ovc_num[(i+1)*V-1 : i*V];
|
assign ivc_info[i].dest_port_encoded=dest_port_encoded[i];
|
assign ivc_info[i].dest_port_encoded=dest_port_encoded[i];
|
//assign ivc_info[i].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[i];
|
//assign ivc_info[i].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[i];
|
//assign ivc_info[i].getting_swa_grant=ivc_num_getting_sw_grant[i];
|
//assign ivc_info[i].getting_swa_grant=ivc_num_getting_sw_grant[i];
|
if(P==MAX_P) begin :max_
|
if(P==MAX_P) begin :max_
|
assign ivc_info[i].destport_one_hot= destport_one_hot[i];
|
assign ivc_info[i].destport_one_hot= destport_one_hot[i];
|
end else begin : no_max
|
end else begin : no_max
|
assign ivc_info[i].destport_one_hot= {{(MAX_P-P){1'b0}},destport_one_hot[i]};
|
assign ivc_info[i].destport_one_hot= {{(MAX_P-P){1'b0}},destport_one_hot[i]};
|
end
|
end
|
//synthesis translate_off
|
//synthesis translate_off
|
//check ivc info
|
//check ivc info
|
//assigned ovc must be onehot coded
|
//assigned ovc must be onehot coded
|
//assert property (@(posedge clk) $onehot0(ivc_info[i].assigned_ovc_num));
|
//assert property (@(posedge clk) $onehot0(ivc_info[i].assigned_ovc_num));
|
always @ (posedge clk )begin
|
always @ (posedge clk )begin
|
if(~ $onehot0(ivc_info[i].assigned_ovc_num)) begin
|
if(~ $onehot0(ivc_info[i].assigned_ovc_num)) begin
|
$display ("ERROR: assigned OVC is not ont-hot coded %d,%m",ivc_info[i].assigned_ovc_num);
|
$display ("ERROR: assigned OVC is not ont-hot coded %d,%m",ivc_info[i].assigned_ovc_num);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
|
|
|
|
|
|
class_ovc_table #(
|
class_ovc_table #(
|
.CVw(CVw),
|
.CVw(CVw),
|
.CLASS_SETTING(CLASS_SETTING),
|
.CLASS_SETTING(CLASS_SETTING),
|
.C(C),
|
.C(C),
|
.V(V)
|
.V(V)
|
)
|
)
|
class_table
|
class_table
|
(
|
(
|
.class_in(class_out[i]),
|
.class_in(class_out[i]),
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
);
|
);
|
|
|
if(PCK_TYPE == "MULTI_FLIT") begin : multi_flit
|
if(PCK_TYPE == "MULTI_FLIT") begin : multi_flit
|
|
|
always @ (*) begin
|
always @ (*) begin
|
ovc_is_assigned_next[i] = ovc_is_assigned[i];
|
ovc_is_assigned_next[i] = ovc_is_assigned[i];
|
if( vsa_ctrl_in.ivc_reset[i] |
|
if( vsa_ctrl_in.ivc_reset[i] |
|
ssa_ctrl_in.ivc_reset[i] |
|
ssa_ctrl_in.ivc_reset[i] |
|
smart_ctrl_in.ivc_reset[i]
|
smart_ctrl_in.ivc_reset[i]
|
) ovc_is_assigned_next[i] = 1'b0;
|
) ovc_is_assigned_next[i] = 1'b0;
|
|
|
else if( vsa_ctrl_in.ivc_num_getting_ovc_grant[i] |
|
else if( vsa_ctrl_in.ivc_num_getting_ovc_grant[i] |
|
(ssa_ctrl_in.ivc_num_getting_ovc_grant[i] & ~ ssa_ctrl_in.ivc_single_flit_pck[i])|
|
(ssa_ctrl_in.ivc_num_getting_ovc_grant[i] & ~ ssa_ctrl_in.ivc_single_flit_pck[i])|
|
(smart_ctrl_in.ivc_num_getting_ovc_grant[i] & ~ smart_ctrl_in.ivc_single_flit_pck[i])
|
(smart_ctrl_in.ivc_num_getting_ovc_grant[i] & ~ smart_ctrl_in.ivc_single_flit_pck[i])
|
) ovc_is_assigned_next[i] = 1'b1;
|
) ovc_is_assigned_next[i] = 1'b1;
|
end//always
|
end//always
|
|
|
|
|
always @(*) begin
|
always @(*) begin
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | smart_ctrl_in.ivc_num_getting_ovc_grant[i] ) begin
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | smart_ctrl_in.ivc_num_getting_ovc_grant[i] ) begin
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
|
end
|
end
|
end
|
end
|
|
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.N (3),
|
.N (3),
|
.W (V)
|
.W (V)
|
) hot_mux (
|
) hot_mux (
|
.in ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
.in ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
smart_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}),
|
smart_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}),
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],smart_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],smart_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
.out (mux_out[i] )
|
.out (mux_out[i] )
|
);
|
);
|
|
|
|
|
/*
|
/*
|
//tail fifo
|
//tail fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(1),
|
.DATA_WIDTH(1),
|
.MAX_DEPTH (PORT_B),
|
.MAX_DEPTH (PORT_B),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
tail_fifo
|
tail_fifo
|
(
|
(
|
.din (tail_flg_in),
|
.din (tail_flg_in),
|
.wr_en (flit_wr[i]), // Write enable
|
.wr_en (flit_wr[i]), // Write enable
|
.rd_en (ivc_num_getting_sw_grant[i]), // Read the next word
|
.rd_en (ivc_num_getting_sw_grant[i]), // Read the next word
|
.dout (flit_is_tail[i]), // Data out
|
.dout (flit_is_tail[i]), // Data out
|
.full ( ),
|
.full ( ),
|
.nearly_full ( ),
|
.nearly_full ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_1 ( ),
|
.recieve_more_than_1 ( ),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
*/
|
*/
|
|
|
end else begin :single_flit
|
end else begin :single_flit
|
//assign flit_is_tail[i]=1'b1;
|
//assign flit_is_tail[i]=1'b1;
|
assign ovc_is_assigned_next[i] = 1'b0;
|
assign ovc_is_assigned_next[i] = 1'b0;
|
|
|
always @(*) begin
|
always @(*) begin
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) begin
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) begin
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
|
assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
|
end
|
end
|
end
|
end
|
|
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.N (2),
|
.N (2),
|
.W (V)
|
.W (V)
|
) hot_mux (
|
) hot_mux (
|
.in ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
.in ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
|
ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}),
|
ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}),
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
.sel ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i]} ),
|
.out (mux_out[i] )
|
.out (mux_out[i] )
|
);
|
);
|
|
|
|
|
|
|
end
|
end
|
//dest_e_addr_in fifo
|
//dest_e_addr_in fifo
|
if(SMART_EN) begin : smart_
|
if(SMART_EN) begin : smart_
|
|
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(EAw),
|
.DATA_WIDTH(EAw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
dest_e_addr_fifo
|
dest_e_addr_fifo
|
(
|
(
|
.din (dest_e_addr_in),
|
.din (dest_e_addr_in),
|
.wr_en (wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en (wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en (rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en (rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout (ivc_info[i].dest_e_addr), // Data out
|
.dout (ivc_info[i].dest_e_addr), // Data out
|
.full ( ),
|
.full ( ),
|
.nearly_full ( ),
|
.nearly_full ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_1 ( ),
|
.recieve_more_than_1 ( ),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
|
|
end else begin : no_smart
|
end else begin : no_smart
|
assign ivc_info[i].dest_e_addr = {EAw{1'bx}};
|
assign ivc_info[i].dest_e_addr = {EAw{1'bx}};
|
end
|
end
|
|
|
|
|
|
|
//class_fifo
|
//class_fifo
|
if(C>1)begin :cb1
|
if(C>1)begin :cb1
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(Cw),
|
.DATA_WIDTH(Cw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
class_fifo
|
class_fifo
|
(
|
(
|
.din (class_in),
|
.din (class_in),
|
.wr_en (wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en (wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en (rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en (rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout (class_out[i]), // Data out
|
.dout (class_out[i]), // Data out
|
.full ( ),
|
.full ( ),
|
.nearly_full ( ),
|
.nearly_full ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_1 ( ),
|
.recieve_more_than_1 ( ),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
|
|
);
|
);
|
end else begin :c_num_1
|
end else begin :c_num_1
|
assign class_out[i] = 1'b0;
|
assign class_out[i] = 1'b0;
|
end
|
end
|
|
|
|
|
//localparam CAST_TYPE = "UNICAST"; // multicast is not yet supported
|
//localparam CAST_TYPE = "UNICAST"; // multicast is not yet supported
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
// for multicast we send one packet to each direction in order. The priority is according to DoR routing dimentions
|
// for multicast we send one packet to each direction in order. The priority is according to DoR routing dimentions
|
|
|
fwft_fifo_with_output_clear #(
|
fwft_fifo_with_output_clear #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(dest_port_multi[i]), // Data out
|
.dout(dest_port_multi[i]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.clear(clear_dspt_mulicast [i]) // clear the destination port once it got the entire packet
|
.clear(clear_dspt_mulicast [i]) // clear the destination port once it got the entire packet
|
);
|
);
|
|
|
//TODO remove multiple_dest[i] to see if it works?
|
//TODO remove multiple_dest[i] to see if it works?
|
|
|
assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};
|
assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}};
|
|
|
// a fix priority arbiter.
|
// a fix priority arbiter.
|
multicast_dst_sel sel(
|
multicast_dst_sel #(
|
|
.NOC_ID(NOC_ID)
|
|
) sel_arb(
|
.destport_in(dest_port_multi[i]),
|
.destport_in(dest_port_multi[i]),
|
.destport_out(dest_port_encoded[i])
|
.destport_out(dest_port_encoded[i])
|
);
|
);
|
|
|
//check if we have multiple port to send a packet to
|
//check if we have multiple port to send a packet to
|
is_onehot0 #(
|
is_onehot0 #(
|
.IN_WIDTH(DSTPw)
|
.IN_WIDTH(DSTPw)
|
)
|
)
|
one_h
|
one_h
|
(
|
(
|
.in(dest_port_multi[i]),
|
.in(dest_port_multi[i]),
|
.result(dst_onhot0[i])
|
.result(dst_onhot0[i])
|
);
|
);
|
assign multiple_dest[i]=~dst_onhot0[i];
|
assign multiple_dest[i]=~dst_onhot0[i];
|
|
|
|
|
end else begin : unicast
|
end else begin : unicast
|
assign multiple_dest[i] = 1'b0;
|
assign multiple_dest[i] = 1'b0;
|
|
|
|
|
//lk_dst_fifo
|
//lk_dst_fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
lk_dest_fifo
|
lk_dest_fifo
|
(
|
(
|
.din (lk_destination_in_encoded),
|
.din (lk_destination_in_encoded),
|
.wr_en (wr_hdr_fwft_fifo_delay [i]), // Write enable
|
.wr_en (wr_hdr_fwft_fifo_delay [i]), // Write enable
|
.rd_en (rd_hdr_fwft_fifo_delay [i]), // Read the next word
|
.rd_en (rd_hdr_fwft_fifo_delay [i]), // Read the next word
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.full (),
|
.full (),
|
.nearly_full (),
|
.nearly_full (),
|
.recieve_more_than_0 (),
|
.recieve_more_than_0 (),
|
.recieve_more_than_1 (),
|
.recieve_more_than_1 (),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
|
|
);
|
);
|
|
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
//destport_fifo
|
//destport_fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[i]), // Data out
|
.dout(dest_port_encoded[i]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
end else begin : adptv_dest
|
end else begin : adptv_dest
|
|
|
fwft_fifo_with_output_clear #(
|
fwft_fifo_with_output_clear #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[i]), // Data out
|
.dout(dest_port_encoded[i]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.clear(destport_clear[i]) // clear other destination ports once one of them is selected
|
.clear(destport_clear[i]) // clear other destination ports once one of them is selected
|
);
|
);
|
|
|
|
|
end
|
end
|
end//unicast
|
end//unicast
|
|
|
|
|
destp_generator #(
|
destp_generator #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.T1(T1),
|
.T1(T1),
|
.NL(T3),
|
.NL(T3),
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.PLw(PLw),
|
.PLw(PLw),
|
.PPSw(PPSw),
|
.PPSw(PPSw),
|
.SELF_LOOP_EN (SELF_LOOP_EN),
|
.SELF_LOOP_EN (SELF_LOOP_EN),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.CAST_TYPE(CAST_TYPE)
|
.CAST_TYPE(CAST_TYPE)
|
)
|
)
|
decoder
|
decoder
|
(
|
(
|
.destport_one_hot (destport_one_hot[i]),
|
.destport_one_hot (destport_one_hot[i]),
|
.dest_port_encoded(dest_port_encoded[i]),
|
.dest_port_encoded(dest_port_encoded[i]),
|
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
.endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
|
.endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
|
.swap_port_presel(swap_port_presel[i]),
|
.swap_port_presel(swap_port_presel[i]),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.odd_column(odd_column)
|
.odd_column(odd_column)
|
);
|
);
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
// the router has multiple local ports. Save the destination local port
|
// the router has multiple local ports. Save the destination local port
|
|
|
|
|
|
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(ELw),
|
.DATA_WIDTH(ELw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
local_dest_fifo
|
local_dest_fifo
|
(
|
(
|
.din(endp_l_in),
|
.din(endp_l_in),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]), // Data out
|
.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]), // Data out
|
.full( ),
|
.full( ),
|
.nearly_full( ),
|
.nearly_full( ),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
|
end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(Pw),
|
.DATA_WIDTH(Pw),
|
.MAX_DEPTH (MAX_PCK),
|
.MAX_DEPTH (MAX_PCK),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
|
)
|
)
|
local_dest_fifo
|
local_dest_fifo
|
(
|
(
|
.din(endp_p_in),
|
.din(endp_p_in),
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.wr_en(wr_hdr_fwft_fifo[i]), // Write enable
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.rd_en(rd_hdr_fwft_fifo[i]), // Read the next word
|
.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]), // Data out
|
.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]), // Data out
|
.full( ),
|
.full( ),
|
.nearly_full( ),
|
.nearly_full( ),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
end else begin : single_local
|
end else begin : single_local
|
assign endp_localp_num[(i+1)*PLw-1 : i*PLw] = {PLw{1'bx}};
|
assign endp_localp_num[(i+1)*PLw-1 : i*PLw] = {PLw{1'bx}};
|
end
|
end
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
/*
|
/*
|
weight_control #(
|
weight_control #(
|
.WEIGHTw(WEIGHTw)
|
.WEIGHTw(WEIGHTw)
|
)
|
)
|
wctrl_per_vc
|
wctrl_per_vc
|
(
|
(
|
.sw_is_granted(ivc_num_getting_sw_grant[i]),
|
.sw_is_granted(ivc_num_getting_sw_grant[i]),
|
.flit_is_tail(flit_is_tail[i]),
|
.flit_is_tail(flit_is_tail[i]),
|
.weight_is_consumed_o(vc_weight_is_consumed[i]),
|
.weight_is_consumed_o(vc_weight_is_consumed[i]),
|
.iport_weight(1), //(iport_weight),
|
.iport_weight(1), //(iport_weight),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
*/
|
*/
|
assign vc_weight_is_consumed[i] = 1'b1;
|
assign vc_weight_is_consumed[i] = 1'b1;
|
end else begin :no_wrra
|
end else begin :no_wrra
|
assign vc_weight_is_consumed[i] = 1'bX;
|
assign vc_weight_is_consumed[i] = 1'bX;
|
end
|
end
|
|
|
end//for i
|
end//for i
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
wire granted_flit_is_tail;
|
wire granted_flit_is_tail;
|
|
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.W(1),
|
.W(1),
|
.N(V)
|
.N(V)
|
)onehot_mux(
|
)onehot_mux(
|
.in(flit_is_tail),
|
.in(flit_is_tail),
|
.out(granted_flit_is_tail),
|
.out(granted_flit_is_tail),
|
.sel(ivc_num_getting_sw_grant)
|
.sel(ivc_num_getting_sw_grant)
|
);
|
);
|
|
|
weight_control#(
|
weight_control#(
|
.ARBITER_TYPE(SWA_ARBITER_TYPE),
|
.ARBITER_TYPE(SWA_ARBITER_TYPE),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.WEIGHTw(WEIGHTw),
|
.WEIGHTw(WEIGHTw),
|
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
|
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
|
.P(P),
|
.P(P),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
wctrl_iport
|
wctrl_iport
|
(
|
(
|
.sw_is_granted(any_ivc_sw_request_granted),
|
.sw_is_granted(any_ivc_sw_request_granted),
|
.flit_is_tail(granted_flit_is_tail),
|
.flit_is_tail(granted_flit_is_tail),
|
.weight_is_consumed_o(iport_weight_is_consumed),
|
.weight_is_consumed_o(iport_weight_is_consumed),
|
.iport_weight(iport_weight),
|
.iport_weight(iport_weight),
|
.oports_weight(oports_weight),
|
.oports_weight(oports_weight),
|
.granted_dest_port(granted_dest_port),
|
.granted_dest_port(granted_dest_port),
|
.refresh_w_counter(refresh_w_counter),
|
.refresh_w_counter(refresh_w_counter),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
|
|
end else begin :no_wrra
|
end else begin :no_wrra
|
assign iport_weight_is_consumed=1'bX;
|
assign iport_weight_is_consumed=1'bX;
|
assign oports_weight = {WP{1'bX}};
|
assign oports_weight = {WP{1'bX}};
|
end
|
end
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
|
if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
|
|
|
|
|
|
/*
|
/*
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if ((ivc_not_empty & flit_is_tail2) != (ivc_not_empty & flit_is_tail))begin
|
if ((ivc_not_empty & flit_is_tail2) != (ivc_not_empty & flit_is_tail))begin
|
$display("ERROR: %b !=%b",flit_is_tail2 , flit_is_tail ) ;
|
$display("ERROR: %b !=%b",flit_is_tail2 , flit_is_tail ) ;
|
$finish;
|
$finish;
|
end
|
end
|
*/
|
*/
|
|
|
|
|
flit_buffer #(
|
flit_buffer #(
|
|
.V(V),
|
.B(PORT_B), // buffer space :flit per VC
|
.B(PORT_B), // buffer space :flit per VC
|
.SSA_EN(SSA_EN)
|
.SSA_EN(SSA_EN),
|
|
.Fw(Fw),
|
|
.PCK_TYPE(PCK_TYPE),
|
|
.CAST_TYPE(CAST_TYPE),
|
|
.DEBUG_EN(DEBUG_EN)
|
)
|
)
|
the_flit_buffer
|
the_flit_buffer
|
(
|
(
|
|
|
.din(flit_in), // Data in
|
.din(flit_in), // Data in
|
.vc_num_wr(vc_num_in),//write virtual channel
|
.vc_num_wr(vc_num_in),//write virtual channel
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read virtual channel
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read virtual channel
|
.wr_en(flit_in_wr), // Write enable
|
.wr_en(flit_in_wr), // Write enable
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.dout(buffer_out), // Data out
|
.dout(buffer_out), // Data out
|
.vc_not_empty(ivc_not_empty),
|
.vc_not_empty(ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
.multiple_dest( multiple_dest ),
|
.multiple_dest( multiple_dest ),
|
.sub_rd_ptr_ld(reset_ivc) ,
|
.sub_rd_ptr_ld(reset_ivc) ,
|
.flit_is_tail(flit_is_tail)
|
.flit_is_tail(flit_is_tail)
|
);
|
);
|
|
|
end else begin :spec//not nonspec comb
|
end else begin :spec//not nonspec comb
|
|
|
|
|
flit_buffer #(
|
flit_buffer #(
|
|
.V(V),
|
.B(PORT_B), // buffer space :flit per VC
|
.B(PORT_B), // buffer space :flit per VC
|
.SSA_EN(SSA_EN)
|
.SSA_EN(SSA_EN),
|
|
.Fw(Fw),
|
|
.PCK_TYPE(PCK_TYPE),
|
|
.CAST_TYPE(CAST_TYPE),
|
|
.DEBUG_EN(DEBUG_EN)
|
)
|
)
|
the_flit_buffer
|
the_flit_buffer
|
(
|
(
|
.din(flit_in), // Data in
|
.din(flit_in), // Data in
|
.vc_num_wr(vc_num_in),//write virtual channel
|
.vc_num_wr(vc_num_in),//write virtual channel
|
.vc_num_rd(ivc_num_getting_sw_grant),//read virtual channel
|
.vc_num_rd(ivc_num_getting_sw_grant),//read virtual channel
|
.wr_en(flit_in_wr), // Write enable
|
.wr_en(flit_in_wr), // Write enable
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.dout(buffer_out), // Data out
|
.dout(buffer_out), // Data out
|
.vc_not_empty(ivc_not_empty),
|
.vc_not_empty(ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
|
.multiple_dest( multiple_dest ),
|
.multiple_dest( multiple_dest ),
|
.sub_rd_ptr_ld(reset_ivc) ,
|
.sub_rd_ptr_ld(reset_ivc) ,
|
.flit_is_tail(flit_is_tail)
|
.flit_is_tail(flit_is_tail)
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(CAST_TYPE== "UNICAST") begin : unicast
|
if(CAST_TYPE== "UNICAST") begin : unicast
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
look_ahead_routing #(
|
look_ahead_routing #(
|
|
.NOC_ID(NOC_ID),
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.T4(T4),
|
.T4(T4),
|
.P(P),
|
.P(P),
|
.RAw(RAw),
|
.RAw(RAw),
|
.EAw(EAw),
|
.EAw(EAw),
|
.DAw(DAw),
|
.DAw(DAw),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE)
|
.ROUTE_TYPE(ROUTE_TYPE)
|
)
|
)
|
lk_routing
|
lk_routing
|
(
|
(
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.neighbors_r_addr(neighbors_r_addr),
|
.neighbors_r_addr(neighbors_r_addr),
|
.dest_e_addr(dest_e_addr_in),
|
.dest_e_addr(dest_e_addr_in),
|
.src_e_addr(src_e_addr_in),
|
.src_e_addr(src_e_addr_in),
|
.destport_encoded(destport_in_encoded),
|
.destport_encoded(destport_in_encoded),
|
.lkdestport_encoded(lk_destination_in_encoded),
|
.lkdestport_encoded(lk_destination_in_encoded),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
end // unicast
|
end // unicast
|
|
|
|
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
header_flit_update_lk_route_ovc #(
|
header_flit_update_lk_route_ovc #(
|
|
.NOC_ID(NOC_ID),
|
.P(P)
|
.P(P)
|
)
|
) the_flit_update (
|
the_flit_update
|
|
(
|
|
.flit_in (buffer_out),
|
.flit_in (buffer_out),
|
.flit_out (flit_out),
|
.flit_out (flit_out),
|
.vc_num_in(ivc_num_getting_sw_grant),
|
.vc_num_in(ivc_num_getting_sw_grant),
|
.lk_dest_all_in (lk_destination_encoded),
|
.lk_dest_all_in (lk_destination_encoded),
|
.assigned_ovc_num (assigned_ovc_num),
|
.assigned_ovc_num (assigned_ovc_num),
|
.any_ivc_sw_request_granted(any_ivc_sw_request_granted),
|
.any_ivc_sw_request_granted(any_ivc_sw_request_granted),
|
.lk_dest_not_registered(lk_destination_in_encoded),
|
.lk_dest_not_registered(lk_destination_in_encoded),
|
.sel (sel),
|
.sel (sel),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
|
|
|
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
//synopsys translate_off
|
//synopsys translate_off
|
generate
|
generate
|
if(DEBUG_EN) begin :debg
|
if(DEBUG_EN) begin :debg
|
|
|
|
|
|
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if((|vsa_ctrl_in.ivc_num_getting_sw_grant) & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
|
if((|vsa_ctrl_in.ivc_num_getting_sw_grant) & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
|
$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
|
$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
|
$finish;
|
$finish;
|
end
|
end
|
end//always
|
end//always
|
|
|
for (i=0;i
|
for (i=0;i
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | (smart_ctrl_in.ivc_num_getting_ovc_grant[i] & (PCK_TYPE == "MULTI_FLIT")) )begin
|
if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | (smart_ctrl_in.ivc_num_getting_ovc_grant[i] & (PCK_TYPE == "MULTI_FLIT")) )begin
|
if( ~ $onehot (mux_out[i])) begin
|
if( ~ $onehot (mux_out[i])) begin
|
$display("%t: ERROR: granted OVC num is not onehot coded %b: %m",$time,mux_out[i]);
|
$display("%t: ERROR: granted OVC num is not onehot coded %b: %m",$time,mux_out[i]);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin
|
if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin
|
$display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
|
$display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
|
$finish;
|
$finish;
|
end
|
end
|
end//always
|
end//always
|
|
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if((dest_port [(i+1)*P_1-1 : i*P_1] == {P_1{1'b0}}) && (ivc_request[i]==1'b1)) begin
|
if((dest_port [(i+1)*P_1-1 : i*P_1] == {P_1{1'b0}}) && (ivc_request[i]==1'b1)) begin
|
$display ("%t: ERROR: The destination port is not set for an active IVC request: %m \n",$time);
|
$display ("%t: ERROR: The destination port is not set for an active IVC request: %m \n",$time);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
end//for
|
end//for
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && CAST_TYPE== "UNICAST") begin : mesh_based
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && CAST_TYPE== "UNICAST") begin : mesh_based
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
debug_mesh_tori_route_ckeck #(
|
debug_mesh_tori_route_ckeck #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.V(V),
|
.V(V),
|
.AVC_ATOMIC_EN(AVC_ATOMIC_EN),
|
.AVC_ATOMIC_EN(AVC_ATOMIC_EN),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.RAw(RAw),
|
.RAw(RAw),
|
.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
|
route_ckeck
|
route_ckeck
|
(
|
(
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.hdr_flg_in(hdr_flg_in),
|
.hdr_flg_in(hdr_flg_in),
|
.flit_in_wr(flit_in_wr),
|
.flit_in_wr(flit_in_wr),
|
.vc_num_in(vc_num_in),
|
.vc_num_in(vc_num_in),
|
.flit_is_tail(flit_is_tail),
|
.flit_is_tail(flit_is_tail),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.dest_e_addr_in(dest_e_addr_in),
|
.dest_e_addr_in(dest_e_addr_in),
|
.src_e_addr_in(src_e_addr_in),
|
.src_e_addr_in(src_e_addr_in),
|
.destport_in(destport_in)
|
.destport_in(destport_in)
|
);
|
);
|
end//mesh
|
end//mesh
|
end//DEBUG_EN
|
end//DEBUG_EN
|
endgenerate
|
endgenerate
|
|
|
`ifdef MONITORE_PATH
|
`ifdef MONITORE_PATH
|
genvar j;
|
genvar j;
|
reg[V-1 :0] t1;
|
reg[V-1 :0] t1;
|
generate
|
generate
|
for (j=0;j
|
for (j=0;j
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(reset)begin
|
if(`pronoc_reset)begin
|
t1[j]<=1'b0;
|
t1[j]<=1'b0;
|
end else begin
|
end else begin
|
if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
|
if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
|
$display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
|
$display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
|
t1[j]<=1;
|
t1[j]<=1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
`endif
|
`endif
|
// synopsys translate_on
|
// synopsys translate_on
|
// synthesis translate_on
|
// synthesis translate_on
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
// decode and mask the destination port according to routing algorithm and topology
|
// decode and mask the destination port according to routing algorithm and topology
|
module destp_generator #(
|
module destp_generator #(
|
parameter TOPOLOGY="MESH",
|
parameter TOPOLOGY="MESH",
|
parameter ROUTE_NAME="XY",
|
parameter ROUTE_NAME="XY",
|
parameter ROUTE_TYPE="DETERMINISTIC",
|
parameter ROUTE_TYPE="DETERMINISTIC",
|
parameter T1=3,
|
parameter T1=3,
|
parameter NL=1,
|
parameter NL=1,
|
parameter P=5,
|
parameter P=5,
|
parameter DSTPw=4,
|
parameter DSTPw=4,
|
parameter PLw=1,
|
parameter PLw=1,
|
parameter PPSw=4,
|
parameter PPSw=4,
|
parameter SW_LOC=0,
|
parameter SW_LOC=0,
|
parameter SELF_LOOP_EN="NO",
|
parameter SELF_LOOP_EN="NO",
|
parameter CAST_TYPE = "UNICAST"
|
parameter CAST_TYPE = "UNICAST"
|
|
|
)
|
)
|
(
|
(
|
destport_one_hot,
|
destport_one_hot,
|
dest_port_encoded,
|
dest_port_encoded,
|
dest_port_out,
|
dest_port_out,
|
endp_localp_num,
|
endp_localp_num,
|
swap_port_presel,
|
swap_port_presel,
|
port_pre_sel,
|
port_pre_sel,
|
odd_column
|
odd_column
|
);
|
);
|
|
|
localparam P_1= ( SELF_LOOP_EN=="NO")? P-1 : P;
|
localparam P_1= ( SELF_LOOP_EN=="NO")? P-1 : P;
|
input [DSTPw-1 : 0] dest_port_encoded;
|
input [DSTPw-1 : 0] dest_port_encoded;
|
input [PLw-1 : 0] endp_localp_num;
|
input [PLw-1 : 0] endp_localp_num;
|
output [P_1-1: 0] dest_port_out;
|
output [P_1-1: 0] dest_port_out;
|
output [P-1 : 0] destport_one_hot;
|
output [P-1 : 0] destport_one_hot;
|
input swap_port_presel;
|
input swap_port_presel;
|
input [PPSw-1 : 0] port_pre_sel;
|
input [PPSw-1 : 0] port_pre_sel;
|
input odd_column;
|
input odd_column;
|
|
|
generate
|
generate
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
if(CAST_TYPE!= "UNICAST") begin : muticast
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
// destination port is not coded for multicast/broadcast
|
// destination port is not coded for multicast/broadcast
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
remove_sw_loc_one_hot #(
|
remove_sw_loc_one_hot #(
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC)
|
)
|
)
|
remove_sw_loc
|
remove_sw_loc
|
(
|
(
|
.destport_in(dest_port_encoded),
|
.destport_in(dest_port_encoded),
|
.destport_out(dest_port_out)
|
.destport_out(dest_port_out)
|
);
|
);
|
end else begin : slp
|
end else begin : slp
|
assign dest_port_out = dest_port_encoded;
|
assign dest_port_out = dest_port_encoded;
|
end
|
end
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if(TOPOLOGY == "FATTREE" ) begin : fat
|
end else if(TOPOLOGY == "FATTREE" ) begin : fat
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
fattree_destp_generator #(
|
fattree_destp_generator #(
|
.K(T1),
|
.K(T1),
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
destp_generator
|
destp_generator
|
(
|
(
|
.dest_port_in_encoded(dest_port_encoded),
|
.dest_port_in_encoded(dest_port_encoded),
|
.dest_port_out(dest_port_out)
|
.dest_port_out(dest_port_out)
|
);
|
);
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if (TOPOLOGY == "TREE") begin :tree
|
end else if (TOPOLOGY == "TREE") begin :tree
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
tree_destp_generator #(
|
tree_destp_generator #(
|
.K(T1),
|
.K(T1),
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
destp_generator
|
destp_generator
|
(
|
(
|
.dest_port_in_encoded(dest_port_encoded),
|
.dest_port_in_encoded(dest_port_encoded),
|
.dest_port_out(dest_port_out)
|
.dest_port_out(dest_port_out)
|
);
|
);
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
|
end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
mesh_torus_destp_generator #(
|
mesh_torus_destp_generator #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.NL(NL),
|
.NL(NL),
|
.PLw(PLw),
|
.PLw(PLw),
|
.PPSw(PPSw),
|
.PPSw(PPSw),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
destp_generator
|
destp_generator
|
(
|
(
|
.dest_port_coded(dest_port_encoded),
|
.dest_port_coded(dest_port_encoded),
|
.endp_localp_num(endp_localp_num),
|
.endp_localp_num(endp_localp_num),
|
.dest_port_out(dest_port_out),
|
.dest_port_out(dest_port_out),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.odd_column(odd_column)// only needed for odd even routing
|
.odd_column(odd_column)// only needed for odd even routing
|
);
|
);
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
end else if (TOPOLOGY == "FMESH") begin :fmesh
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
fmesh_destp_generator #(
|
fmesh_destp_generator #(
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.NL(NL),
|
.NL(NL),
|
.PLw(PLw),
|
.PLw(PLw),
|
.PPSw(PPSw),
|
.PPSw(PPSw),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
destp_generator
|
destp_generator
|
(
|
(
|
.dest_port_coded(dest_port_encoded),
|
.dest_port_coded(dest_port_encoded),
|
.endp_localp_num(endp_localp_num),
|
.endp_localp_num(endp_localp_num),
|
.dest_port_out(dest_port_out),
|
.dest_port_out(dest_port_out),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.odd_column(odd_column) // only needed for odd even routing
|
.odd_column(odd_column) // only needed for odd even routing
|
);
|
);
|
end else begin :custom
|
end else begin :custom
|
|
|
custom_topology_destp_decoder #(
|
custom_topology_destp_decoder #(
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
destp_generator
|
destp_generator
|
(
|
(
|
.dest_port_in_encoded(dest_port_encoded),
|
.dest_port_in_encoded(dest_port_encoded),
|
.dest_port_out(dest_port_out)
|
.dest_port_out(dest_port_out)
|
);
|
);
|
end
|
end
|
|
|
if(SELF_LOOP_EN=="NO") begin : nslp
|
if(SELF_LOOP_EN=="NO") begin : nslp
|
add_sw_loc_one_hot #(
|
add_sw_loc_one_hot #(
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC)
|
)add
|
)add
|
(
|
(
|
.destport_in(dest_port_out),
|
.destport_in(dest_port_out),
|
.destport_out(destport_one_hot)
|
.destport_out(destport_one_hot)
|
);
|
);
|
|
|
end else begin : slp
|
end else begin : slp
|
assign destport_one_hot = dest_port_out;
|
assign destport_one_hot = dest_port_out;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
/******************
|
/******************
|
* custom_topology_destp_decoder
|
* custom_topology_destp_decoder
|
* ***************/
|
* ***************/
|
|
|
|
|
module custom_topology_destp_decoder #(
|
module custom_topology_destp_decoder #(
|
parameter ROUTE_TYPE="DETERMINISTIC",
|
parameter ROUTE_TYPE="DETERMINISTIC",
|
parameter DSTPw=4,
|
parameter DSTPw=4,
|
parameter P=5,
|
parameter P=5,
|
parameter SW_LOC=0,
|
parameter SW_LOC=0,
|
parameter SELF_LOOP_EN="NO"
|
parameter SELF_LOOP_EN="NO"
|
)(
|
)(
|
dest_port_in_encoded,
|
dest_port_in_encoded,
|
dest_port_out
|
dest_port_out
|
);
|
);
|
|
|
localparam
|
localparam
|
P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
|
P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
|
MAXW =2**DSTPw;
|
MAXW =2**DSTPw;
|
|
|
input [DSTPw-1 : 0] dest_port_in_encoded;
|
input [DSTPw-1 : 0] dest_port_in_encoded;
|
output [P_1-1 : 0] dest_port_out;
|
output [P_1-1 : 0] dest_port_out;
|
|
|
|
|
wire [MAXW-1 : 0] dest_port_one_hot;
|
wire [MAXW-1 : 0] dest_port_one_hot;
|
|
|
bin_to_one_hot #(
|
bin_to_one_hot #(
|
.BIN_WIDTH(DSTPw),
|
.BIN_WIDTH(DSTPw),
|
.ONE_HOT_WIDTH(MAXW)
|
.ONE_HOT_WIDTH(MAXW)
|
)
|
)
|
conv
|
conv
|
(
|
(
|
.bin_code(dest_port_in_encoded),
|
.bin_code(dest_port_in_encoded),
|
.one_hot_code(dest_port_one_hot)
|
.one_hot_code(dest_port_one_hot)
|
);
|
);
|
generate
|
generate
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
if( SELF_LOOP_EN=="NO") begin : nslp
|
remove_sw_loc_one_hot #(
|
remove_sw_loc_one_hot #(
|
.P(P),
|
.P(P),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC)
|
)
|
)
|
remove_sw_loc
|
remove_sw_loc
|
(
|
(
|
.destport_in(dest_port_one_hot[P-1 : 0]),
|
.destport_in(dest_port_one_hot[P-1 : 0]),
|
.destport_out(dest_port_out)
|
.destport_out(dest_port_out)
|
);
|
);
|
end else begin : slp
|
end else begin : slp
|
assign dest_port_out = dest_port_one_hot;
|
assign dest_port_out = dest_port_one_hot;
|
end
|
end
|
endgenerate
|
endgenerate
|
//synthesis translate_off
|
//synthesis translate_off
|
//synopsys translate_off
|
//synopsys translate_off
|
|
|
initial begin
|
initial begin
|
if( ROUTE_TYPE != "DETERMINISTIC") begin
|
if( ROUTE_TYPE != "DETERMINISTIC") begin
|
$display("%t: ERROR: Custom topologies can only support deterministic routing in the current version of ProNoC",$time);
|
$display("%t: ERROR: Custom topologies can only support deterministic routing in the current version of ProNoC",$time);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
|
|
|
|
//synopsys translate_on
|
//synopsys translate_on
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
endmodule
|
endmodule
|
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