| Line 110... |
Line 110... |
input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
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input smart_ctrl_t smart_ctrl_in [P-1: 0];
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input smart_ctrl_t smart_ctrl_in [P-1: 0];
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input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
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input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
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wire [PVV-1 : 0] ssa_granted_ovc_num_all;
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logic [PV-1 : 0] ovc_status;
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logic [PV-1 : 0] ovc_status;
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logic [PV-1 : 0] ovc_status_next;
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logic [PV-1 : 0] ovc_status_next;
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wire [PV-1 : 0] assigned_ovc_is_full_all;
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wire [PV-1 : 0] assigned_ovc_is_full_all;
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wire [VP_1-1 : 0] credit_decreased [P-1 : 0];
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wire [VP_1-1 : 0] credit_decreased [P-1 : 0];
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wire [P_1-1 : 0] credit_decreased_gen [PV-1 : 0];
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wire [P_1-1 : 0] credit_decreased_gen [PV-1 : 0];
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| Line 194... |
Line 196... |
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// wire [PV-1 : 0] non_smart_ovc_allocated_all = ssa_ovc_allocated_all| vsa_ovc_allocated_all;
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// wire [PV-1 : 0] non_smart_ovc_allocated_all = ssa_ovc_allocated_all| vsa_ovc_allocated_all;
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wire [PV-1 : 0] non_smart_ovc_allocated_all;
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wire [PV-1 : 0] non_smart_ovc_allocated_all;
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generate
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generate
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for(i=0;i
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for(i=0;i
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assign ssa_granted_ovc_num_all[(i+1)*VV-1: i*VV] = ssa_ctrl_in[i].ivc_granted_ovc_num;
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assign credit_decreased_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].buff_space_decreased | ssa_ctrl_in[i].buff_space_decreased | smart_ctrl_in[i].buff_space_decreased;
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assign credit_decreased_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].buff_space_decreased | ssa_ctrl_in[i].buff_space_decreased | smart_ctrl_in[i].buff_space_decreased;
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assign ovc_released_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_released | ssa_ctrl_in[i].ovc_is_released | smart_ctrl_in[i].ovc_is_released;
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assign ovc_released_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_released | ssa_ctrl_in[i].ovc_is_released | smart_ctrl_in[i].ovc_is_released;
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assign ovc_allocated_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_allocated | ssa_ctrl_in[i].ovc_is_allocated | smart_ctrl_in[i].ovc_is_allocated;
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assign ovc_allocated_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_allocated | ssa_ctrl_in[i].ovc_is_allocated | smart_ctrl_in[i].ovc_is_allocated;
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//assign non_smart_ovc_allocated_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ovc_is_allocated | vsa_ctrl_in[i].ovc_is_allocated;
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//assign non_smart_ovc_allocated_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ovc_is_allocated | vsa_ctrl_in[i].ovc_is_allocated;
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| Line 282... |
Line 284... |
assign nearly_full_perport [i]=nearly_full_all;
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assign nearly_full_perport [i]=nearly_full_all;
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end
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end
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end
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end
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for(i=0; i
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for(i=0; i
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assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[i/V][i%V].assigned_ovc_num;
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assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[i/V][i%V].assigned_ovc_num;
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assign ovc_is_assigned_all[i]=ivc_info[i/V][i%V].ovc_is_assigned;
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assign ovc_is_assigned_all[i]=ivc_info[i/V][i%V].ovc_is_assigned;
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| Line 317... |
Line 323... |
.SELF_LOOP_EN (SELF_LOOP_EN)
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.SELF_LOOP_EN (SELF_LOOP_EN)
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)
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)
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sw_mask
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sw_mask
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(
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(
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.ssa_granted_ovc_num(ssa_granted_ovc_num_all[(i+1)*V-1 :i*V]),
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.granted_ovc_num(granted_ovc_num_all[(i+1)*V-1 :i*V]),
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.granted_ovc_num(granted_ovc_num_all[(i+1)*V-1 :i*V]),
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.ovc_is_assigned(ovc_is_assigned_all[i]),
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.ovc_is_assigned(ovc_is_assigned_all[i]),
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.assigned_ovc_num (assigned_ovc_num_all[(i+1)*V-1 :i*V]),
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.assigned_ovc_num (assigned_ovc_num_all[(i+1)*V-1 :i*V]),
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.dest_port (dest_port_all [(i+1)*P_1-1 :i*P_1]),
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.dest_port (dest_port_all [(i+1)*P_1-1 :i*P_1]),
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.full (full_perport [i/V]),
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.full (full_perport [i/V]),
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| Line 646... |
Line 653... |
parameter P = 5, // router port num
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parameter P = 5, // router port num
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parameter OVC_ALLOC_MODE=1'b0,
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parameter OVC_ALLOC_MODE=1'b0,
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parameter SELF_LOOP_EN = "NO"
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parameter SELF_LOOP_EN = "NO"
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)(
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)(
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ssa_granted_ovc_num,
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granted_ovc_num,
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granted_ovc_num,
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ovc_is_assigned,
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ovc_is_assigned,
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assigned_ovc_num,
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assigned_ovc_num,
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dest_port,
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dest_port,
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full,
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full,
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| Line 662... |
Line 670... |
);
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);
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localparam P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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localparam P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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VP_1 = V * P_1;
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VP_1 = V * P_1;
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input clk,reset;
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input clk,reset;
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input ovc_is_assigned;
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input ovc_is_assigned;
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input [V-1 : 0] assigned_ovc_num,granted_ovc_num;
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input [V-1 : 0] assigned_ovc_num,granted_ovc_num,ssa_granted_ovc_num;
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input [P_1-1 : 0] dest_port;
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input [P_1-1 : 0] dest_port;
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input [VP_1-1 : 0] full;
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input [VP_1-1 : 0] full;
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input [VP_1-1 : 0] credit_increased;
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input [VP_1-1 : 0] credit_increased;
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input [VP_1-1 : 0] nearly_full;
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input [VP_1-1 : 0] nearly_full;
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input ivc_getting_sw_grant;
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input ivc_getting_sw_grant;
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| Line 714... |
Line 722... |
.in (full_muxout1),
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.in (full_muxout1),
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.out (full_muxout2),
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.out (full_muxout2),
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.sel (assigned_ovc_num)
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.sel (assigned_ovc_num)
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);
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);
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wire [V-1 : 0] nearlyfull_sel = (ovc_is_assigned | ~OVC_ALLOC_MODE)? assigned_ovc_num : granted_ovc_num;
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wire [V-1 : 0] nearlyfull_sel = (ovc_is_assigned | ~OVC_ALLOC_MODE)? assigned_ovc_num : granted_ovc_num ;// or (granted_ovc_num | ssa_granted_ovc_num) ?
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onehot_mux_1D #(
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onehot_mux_1D #(
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.W (1),
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.W (1),
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.N (V)
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.N (V)
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)nearlfull_mux2
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)nearlfull_mux2
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