| Line 1... |
Line 1... |
`timescale 1ns/1ps
|
`include "pronoc_def.v"
|
|
|
/****************************
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/****************************
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* This module can inject and eject packets from the NoC.
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* This module can inject and eject packets from the NoC.
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* It can be used in simulation for injecting real application traces to the NoC
|
* It can be used in simulation for injecting real application traces to the NoC
|
* *************************/
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* *************************/
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|
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| Line 45... |
Line 46... |
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|
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assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
|
assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
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|
|
|
|
|
generate if(CAST_TYPE == "UNICAST") begin : uni
|
|
|
conventional_routing #(
|
conventional_routing #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_NAME(ROUTE_NAME),
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.ROUTE_TYPE(ROUTE_TYPE),
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.ROUTE_TYPE(ROUTE_TYPE),
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| Line 68... |
Line 69... |
.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.dest_e_addr(pck_injct_in.endp_addr),
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.dest_e_addr(pck_injct_in.endp_addr),
|
.src_e_addr(current_e_addr),
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.src_e_addr(current_e_addr),
|
.destport(destport)
|
.destport(destport)
|
);
|
);
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end endgenerate
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|
|
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localparam
|
localparam
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
|
HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
|
HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
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HDR_DATA_w =
|
|
(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
|
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(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;
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|
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wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
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wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
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wire [Fw-1 : 0] hdr_flit_out;
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wire [Fw-1 : 0] hdr_flit_out;
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|
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header_flit_generator #(
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header_flit_generator #(
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| Line 103... |
Line 108... |
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
|
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
|
CNTw = log2(REMAIN_DAT_FLIT),
|
CNTw = log2(REMAIN_DAT_FLIT),
|
MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
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MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
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reg [PCK_SIZw-1 : 0] counter, counter_next;
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logic [PCK_SIZw-1 : 0] counter, counter_next;
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reg [CNTw-1 : 0] counter2,counter2_next;
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logic [CNTw-1 : 0] counter2,counter2_next;
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reg tail,head;
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reg tail,head;
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|
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wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];
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wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];
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wire [Fpay-1 : 0] dataIn = remain_dat[counter2];
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wire [Fpay-1 : 0] dataIn = remain_dat[counter2];
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enum {HEADER, BODY,TAIL} flit_type,flit_type_next;
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enum bit [2:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;
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wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};
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wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};
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wire [V-1 : 0] vc_fifo_full;
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wire [V-1 : 0] vc_fifo_full;
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| Line 124... |
Line 129... |
localparam
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localparam
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LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
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LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
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LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
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LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
|
genvar i;
|
genvar i;
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generate
|
generate
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for(i=0; i
|
for(i=0; i
|
assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1 : (Fpay*i)+HDR_DATA_w];
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assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1 : (Fpay*i)+HDR_DATA_w];
|
end
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end
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if(REMAIN_DAT_FLIT_F ) begin
|
if(REMAIN_DAT_FLIT_F ) begin :flt
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|
|
assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
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assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
|
end
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end
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endgenerate
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endgenerate
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| Line 186... |
Line 191... |
TAIL: begin
|
TAIL: begin
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flit_type_next = HEADER;
|
flit_type_next = HEADER;
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flit_wr=1;
|
flit_wr=1;
|
tail=1'b1;
|
tail=1'b1;
|
end
|
end
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endcase
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default: begin
|
|
|
end
|
end
|
end
|
endcase
|
reg [V-1 : 0] credit_o;
|
|
|
|
always @ (posedge clk) begin
|
|
if(reset) begin
|
|
flit_type<=HEADER;
|
|
counter<=0;
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|
counter2<=0;
|
|
credit_o<={V{1'b0}};
|
|
end else begin
|
|
flit_type<=flit_type_next;
|
|
counter<=counter_next;
|
|
counter2<=counter2_next;
|
|
if (chan_in.flit_chanel.flit_wr) credit_o<= chan_in.flit_chanel.flit.vc;
|
|
else credit_o<={V{1'b0}};
|
|
end
|
end
|
end
|
end
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|
|
|
logic [V-1 : 0] credit_o, credit_o_next;
|
|
|
|
//pronoc_register #(.W(3),.RESET_TO(HEADER) ) reg1 (.in(flit_type_next ), .out(flit_type), .reset(reset), .clk(clk));
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pronoc_register #(.W(PCK_SIZw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
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pronoc_register #(.W(CNTw)) reg3 (.in(counter2_next ), .out(counter2), .reset(reset), .clk(clk));
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pronoc_register #(.W(V)) reg4 (.in(credit_o_next ), .out(credit_o), .reset(reset), .clk(clk));
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|
|
|
|
|
always @ (*) begin
|
|
credit_o_next = credit_o;
|
|
if (chan_in.flit_chanel.flit_wr) credit_o_next = chan_in.flit_chanel.flit.vc;
|
|
else credit_o_next = {V{1'b0}};
|
|
end
|
|
|
|
always @(`pronoc_clk_reset_edge)begin
|
|
if(`pronoc_reset) flit_type<=HEADER;
|
|
else flit_type <= flit_type_next;
|
|
end
|
|
|
|
|
|
|
injector_ovc_status #(
|
injector_ovc_status #(
|
.V(V),
|
.V(V),
|
| Line 262... |
Line 271... |
|
|
//synthesis translate_off
|
//synthesis translate_off
|
wire [NEw-1 : 0] current_id;
|
wire [NEw-1 : 0] current_id;
|
wire [NEw-1 : 0] sendor_id;
|
wire [NEw-1 : 0] sendor_id;
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr));
|
endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
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//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
wire [NE-1 :0] dest_mcast_all_endp;
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|
|
|
|
|
|
|
|
generate
|
generate
|
|
if(CAST_TYPE != "UNICAST") begin
|
|
mcast_dest_list_decode decode (
|
|
.dest_e_addr(hdr_flit_i.dest_e_addr),
|
|
.dest_o(dest_mcast_all_endp),
|
|
.row_has_any_dest(),
|
|
.is_unicast()
|
|
);
|
|
end
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|
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for(i=0; i
|
for(i=0; i
|
always@(*) begin
|
always@(*) begin
|
h2t_counter_next[i]=h2t_counter[i]+1'b1;
|
h2t_counter_next[i]=h2t_counter[i]+1'b1;
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
|
h2t_counter_next[i]= 16'd0; // reset once header flit is received
|
h2t_counter_next[i]= 16'd0; // reset once header flit is received
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| Line 278... |
Line 300... |
end//always
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end//always
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|
|
|
|
|
always_ff @(posedge clk or posedge reset) begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if (reset) begin
|
if(`pronoc_reset) begin
|
rsv_counter[i]<= {PCK_SIZw{1'b0}};
|
rsv_counter[i]<= {PCK_SIZw{1'b0}};
|
h2t_counter[i]<= 16'd0;
|
h2t_counter[i]<= 16'd0;
|
sender_endp_addr_reg [i]<= {EAw{1'b0}};
|
sender_endp_addr_reg [i]<= {EAw{1'b0}};
|
end else begin
|
end else begin
|
h2t_counter[i]<=h2t_counter_next[i];
|
h2t_counter[i]<=h2t_counter_next[i];
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if(chan_in.flit_chanel.flit.hdr_flag)begin
|
if(chan_in.flit_chanel.flit.hdr_flag)begin
|
rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
|
rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
|
sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
|
sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
|
//synthesis translate_off
|
//synthesis translate_off
|
if(hdr_flit_i.dest_e_addr != current_e_addr) begin
|
if(CAST_TYPE == "UNICAST") begin
|
|
if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin
|
$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
|
$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
|
$finish;
|
$finish;
|
end//if hdr_flit_i
|
end//if hdr_flit_i
|
|
end else begin
|
|
if(dest_mcast_all_endp[current_id] !=1'b1 ) begin
|
|
$display("%t: ERROR: packet destination address %b does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
|
|
$finish;
|
|
end
|
|
end//if hdr_flit_i
|
//synthesis translate_on
|
//synthesis translate_on
|
end //if hdr_flag
|
end //if hdr_flag
|
else rsv_counter[i]<= rsv_counter[i]+1'b1;
|
else rsv_counter[i]<= rsv_counter[i]+1'b1;
|
end//flit wr
|
end//flit wr
|
end//reset
|
end//reset
|
| Line 306... |
Line 335... |
|
|
|
|
|
|
for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
|
for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
|
|
|
always_ff @(posedge clk or posedge reset) begin
|
always @ (`pronoc_clk_reset_edge )begin
|
if (reset) begin
|
if(`pronoc_reset) begin
|
pck_data_o_gen [i][k] <= {Fpay{1'b0}};
|
pck_data_o_gen [i][k] <= {Fpay{1'b0}};
|
|
|
end else begin
|
end else begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
|
if (chan_in.flit_chanel.flit.hdr_flag )begin
|
if (chan_in.flit_chanel.flit.hdr_flag )begin
|
if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
|
if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
|
end
|
end
|
else begin
|
else begin
|
if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;
|
if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];
|
|
|
end // else
|
end // else
|
end //if
|
end //if
|
end //else
|
end //else
|
end// always
|
end// always
|
| Line 350... |
Line 379... |
|
|
wire [V-1 : 0] vc_reg;
|
wire [V-1 : 0] vc_reg;
|
wire tail_flag_reg, hdr_flag_reg;
|
wire tail_flag_reg, hdr_flag_reg;
|
|
|
|
|
register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));
|
pronoc_register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));
|
register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));
|
pronoc_register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));
|
register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));
|
pronoc_register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));
|
|
|
wire [Vw-1 : 0] vc_bin;
|
wire [Vw-1 : 0] vc_bin;
|
|
|
one_hot_to_bin #(
|
one_hot_to_bin #(
|
.ONE_HOT_WIDTH (V),
|
.ONE_HOT_WIDTH (V),
|
| Line 369... |
Line 398... |
|
|
assign pck_injct_out.data = pck_data_o[vc_bin];
|
assign pck_injct_out.data = pck_data_o[vc_bin];
|
assign pck_injct_out.size = rsv_counter[vc_bin];
|
assign pck_injct_out.size = rsv_counter[vc_bin];
|
assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
|
assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
|
assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};
|
assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};
|
assign pck_injct_out.endp_addr = sender_endp_addr_reg[vc_bin];
|
assign pck_injct_out.endp_addr[EAw-1 : 0] = sender_endp_addr_reg[vc_bin];
|
assign pck_injct_out.vc = vc_reg;
|
assign pck_injct_out.vc = vc_reg;
|
assign pck_injct_out.pck_wr = tail_flag_reg;
|
assign pck_injct_out.pck_wr = tail_flag_reg;
|
|
|
assign chan_out.flit_chanel.flit.hdr_flag =head;
|
assign chan_out.flit_chanel.flit.hdr_flag =head;
|
assign chan_out.flit_chanel.flit.tail_flag=tail;
|
assign chan_out.flit_chanel.flit.tail_flag=tail;
|
assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
|
assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
|
assign chan_out.flit_chanel.flit_wr=flit_wr;
|
assign chan_out.flit_chanel.flit_wr=flit_wr;
|
|
|
|
generate
|
|
/* verilator lint_off WIDTH */
|
|
if(PCK_TYPE == "SINGLE_FLIT" ) begin : single_f
|
|
/* verilator lint_on WIDTH */
|
|
assign chan_out.flit_chanel.flit.payload = hdr_flit_out[FPAYw-1 : 0];
|
|
end else begin
|
assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
|
assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
|
|
end
|
|
endgenerate
|
|
|
assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
|
assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
|
assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
|
assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
|
assign chan_out.flit_chanel.credit= credit_o;
|
assign chan_out.flit_chanel.credit= credit_o;
|
assign chan_out.ctrl_chanel.credit_init_val= LB;
|
assign chan_out.ctrl_chanel.credit_init_val= LB;
|
|
assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
|
|
assign chan_out.ctrl_chanel.endp_port =1'b1;
|
|
|
|
|
|
|
distance_gen #(
|
distance_gen #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
| Line 493... |
Line 533... |
|
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for(i=0;i
|
for(i=0;i
|
`ifdef SYNC_RESET_MODE
|
always @ (`pronoc_clk_reset_edge )begin
|
always @ (posedge clk )begin
|
if(`pronoc_reset) begin
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
if(reset)begin
|
|
credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
|
credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
|
end else begin
|
end else begin
|
if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
|
if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;
|
if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
|
if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;
|
end //reset
|
end //reset
|
| Line 572... |
Line 608... |
//control interafce
|
//control interafce
|
|
|
|
|
input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
|
input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
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input [PCK_SIZw-1 : 0] pck_injct_in_size;
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input [PCK_SIZw-1 : 0] pck_injct_in_size;
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input [EAw-1 : 0] pck_injct_in_endp_addr;
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input [DAw-1 : 0] pck_injct_in_endp_addr;
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input [Cw-1 : 0] pck_injct_in_class_num;
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input [Cw-1 : 0] pck_injct_in_class_num;
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input [WEIGHTw-1 : 0] pck_injct_in_init_weight;
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input [WEIGHTw-1 : 0] pck_injct_in_init_weight;
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input [V-1 : 0] pck_injct_in_vc;
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input [V-1 : 0] pck_injct_in_vc;
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input pck_injct_in_pck_wr;
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input pck_injct_in_pck_wr;
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input [V-1 : 0] pck_injct_in_ready;
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input [V-1 : 0] pck_injct_in_ready;
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|
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output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
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output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
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output [PCK_SIZw-1 : 0] pck_injct_out_size;
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output [PCK_SIZw-1 : 0] pck_injct_out_size;
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output [EAw-1 : 0] pck_injct_out_endp_addr;
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output [DAw-1 : 0] pck_injct_out_endp_addr;
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output [Cw-1 : 0] pck_injct_out_class_num;
|
output [Cw-1 : 0] pck_injct_out_class_num;
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output [WEIGHTw-1 : 0] pck_injct_out_init_weight;
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output [WEIGHTw-1 : 0] pck_injct_out_init_weight;
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output [V-1 : 0] pck_injct_out_vc;
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output [V-1 : 0] pck_injct_out_vc;
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output pck_injct_out_pck_wr;
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output pck_injct_out_pck_wr;
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output [V-1 : 0] pck_injct_out_ready;
|
output [V-1 : 0] pck_injct_out_ready;
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| Line 627... |
Line 663... |
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localparam
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localparam
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HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
|
HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
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HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
|
HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
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HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,
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HDR_DATA_w =
|
|
(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
|
|
(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp,
|
REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
|
REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,
|
REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
|
REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
|
REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
|
REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
|
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
|
REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
|
CNTw = log2(REMAIN_DAT_FLIT),
|
CNTw = log2(REMAIN_DAT_FLIT),
|
