URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [ram_test_top.v] - Diff between revs 38 and 48

Rev 38	Rev 48
Line 56...	Line 56...
`end`	`end`
`i2s = tmp[15:0];`	`i2s = tmp[15:0];`
`end`	`end`
`endfunction //i2s`	`endfunction //i2s`

`localparam programer_DW=32;`	`localparam programmer_DW=32;`
`localparam programer_AW=32;`	`localparam programmer_AW=32;`
`localparam programer_S_Aw= 7;`	`localparam programmer_S_Aw= 7;`
`localparam programer_M_Aw= 32;`	`localparam programmer_M_Aw= 32;`
`localparam programer_TAGw= 3;`	`localparam programmer_TAGw= 3;`
`localparam programer_SELw= 4;`	`localparam programmer_SELw= 4;`
`localparam programer_VJTAG_INDEX=CORE_ID;`	`localparam programmer_VJTAG_INDEX=CORE_ID;`

`localparam ram_BYTE_WR_EN="YES";`	`localparam ram_BYTE_WR_EN="YES";`
`localparam ram_FPGA_VENDOR="ALTERA";`	`localparam ram_FPGA_VENDOR="ALTERA";`
`localparam ram_JTAG_CONNECT= "ALTERA_IMCE";`	`localparam ram_JTAG_CONNECT= "ALTERA_IMCE";`
`localparam ram_JTAG_INDEX=CORE_ID;`	`localparam ram_JTAG_INDEX=CORE_ID;`