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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [sw/] [link.ld] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 1... Line 1...
OUTPUT_ARCH(or1knd)
OUTPUT_ARCH(or1knd)
SEARCH_DIR(.)
SEARCH_DIR(.)
__DYNAMIC  =  0;
__DYNAMIC  =  0;
 
 
MEMORY
INCLUDE linkvar.ld;
{
 
        vectors : ORIGIN = 0, LENGTH = 0x1000
 
        ram     : ORIGIN = 0x1000, LENGTH = (8M - 0x1000)
 
}
 
 
 
 
 
/* Stack information variables */
/* Stack information variables */
_min_stack      = 0x2000;   /* 8K - minimum stack space to reserve */
_min_stack      = 0x2000;   /* 8K - minimum stack space to reserve */
 
 
Line 16... Line 13...
SECTIONS
SECTIONS
{
{
        .vectors :
        .vectors :
        {
        {
                *(.vectors)
                *(.vectors)
        } > vectors
        } > rom
 
 
        .text : {
        .text 0x1000 : {
                _stext = .;
                _stext = .;
                *(.text)
                *(.text)
                _etext  =  .;
                _etext  =  .;
                __CTOR_LIST__ = .;
                __CTOR_LIST__ = .;
                LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
                LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
Line 35... Line 32...
                LONG(0)
                LONG(0)
                __DTOR_END__ = .;
                __DTOR_END__ = .;
                *(.lit)
                *(.lit)
                *(.shdata)
                *(.shdata)
                _endtext = .;
                _endtext = .;
        }  > ram
        }  > rom
 
 
        .rodata : {
        .rodata : {
 
                _srodata = .;
                *(.rodata);
                *(.rodata);
                *(.rodata.*)
                *(.rodata.*)
        } > ram
                . = ALIGN(0x10);
 
                _erodata = .;
 
        } > rom
 
 
        .shbss :
        .shbss :
        {
        {
                *(.shbss)
                *(.shbss)
        } > ram
        } > ram
Line 56... Line 56...
        .data : {
        .data : {
                sdata  =  .;
                sdata  =  .;
                _sdata  =  .;
                _sdata  =  .;
                *(.data)
                *(.data)
                edata  =  .;
                edata  =  .;
 
                . = ALIGN(0x4);
                _edata  =  .;
                _edata  =  .;
        } > ram
        } > ram AT > rom  /* "> ram" is the VMA, "> rom" is the LMA */
 
 
        .bss :
        .bss :
        {
        {
                _bss_start = .;
                _bss_start = .;
                *(.bss)
                *(.bss)

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