### Description
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### Description
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The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
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The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
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The core was modeled and tested based on the Bochs software x86 implementation.
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The core was modeled and tested based on the Bochs software x86 implementation.
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Together with the 486 core, the ao486 project also contains a SoC capable of
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Together with the 486 core, the ao486 project also contains a SoC capable of
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booting the Linux kernel version 3.13 and Microsoft Windows 95.
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booting the Linux kernel version 3.13 and Microsoft Windows 95.
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### Features
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### Features
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The ao486 processor model has the following features:
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The ao486 processor model has the following features:
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- pipeline architecture with 4 main stages: decode, read, execute and write,
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- pipeline architecture with 4 main stages: decode, read, execute and write,
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- all 486 instructions are implemented, together with CPUID,
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- all 486 instructions are implemented, together with CPUID,
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- 16 kB instruction cache,
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- 16 kB instruction cache,
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- 16 kB write-back data cache,
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- 16 kB write-back data cache,
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- TLB for 32 entries,
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- TLB for 32 entries,
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- Altera Avalon interfaces for memory and io access.
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- Altera Avalon interfaces for memory and io access.
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The ao486 SoC consists of the following components:
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The ao486 SoC consists of the following components:
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- ao486 processor,
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- ao486 processor,
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- IDE hard drive that redirects to a HDL SD card driver,
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- IDE hard drive that redirects to a HDL SD card driver,
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- floppy controller that also redirects to the SD card driver,
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- floppy controller that also redirects to the SD card driver,
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- 8259 PIC,
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- 8259 PIC,
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- 8237 DMA,
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- 8237 DMA,
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- Sound Blaster 2.0 with DSP and OPL2 (FM synthesis not fully working).
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- Sound Blaster 2.0 with DSP and OPL2 (FM synthesis not fully working).
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Sound output redirected to a WM8731 audio codec,
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Sound output redirected to a WM8731 audio codec,
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- 8254 PIT,
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- 8254 PIT,
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- 8042 keyboard and mouse controller,
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- 8042 keyboard and mouse controller,
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- RTC
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- RTC
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- standard VGA.
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- standard VGA.
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All components are modeled as Altera Qsys components. Altera Qsys connects all
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All components are modeled as Altera Qsys components. Altera Qsys connects all
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parts together, and supplies the SDRAM controller.
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parts together, and supplies the SDRAM controller.
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The ao486 project is currently only running on the Terasic DE2-115 board.
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The ao486 project is currently only running on the Terasic DE2-115 board.
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### Resource usage
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### Resource usage
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The project is synthesised for the Altera Cyclone IV E EP4CE115F29C7 device.
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The project is synthesised for the Altera Cyclone IV E EP4CE115F29C7 device.
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Resource utilization is as follows:
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Resource utilization is as follows:
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| Unit | Logic cells | M9K memory blocks |
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| Unit | Logic cells | M9K memory blocks |
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|--------------------|-------------|-------------------|
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|--------------------|-------------|-------------------|
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| ao486 processor | 36517 | 47 |
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| ao486 processor | 36517 | 47 |
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| floppy | 1514 | 2 |
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| floppy | 1514 | 2 |
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| hdd | 2071 | 17 |
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| hdd | 2071 | 17 |
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| nios2 | 1056 | 3 |
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| nios2 | 1056 | 3 |
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| onchip for nios2 | 0 | 32 |
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| onchip for nios2 | 0 | 32 |
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| pc_dma | 848 | 0 |
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| pc_dma | 848 | 0 |
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| pic | 388 | 0 |
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| pic | 388 | 0 |
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| pit | 667 | 0 |
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| pit | 667 | 0 |
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| ps2 | 742 | 2 |
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| ps2 | 742 | 2 |
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| rtc | 783 | 1 |
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| rtc | 783 | 1 |
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| sound | 37131 | 29 |
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| sound | 37131 | 29 |
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| vga | 2534 | 260 |
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| vga | 2534 | 260 |
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The fitter raport after compiling all components of the ao486 project is as
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The fitter raport after compiling all components of the ao486 project is as
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follows:
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follows:
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```
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```
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Fitter Status : Successful - Sun Mar 30 21:00:13 2014
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Fitter Status : Successful - Sun Mar 30 21:00:13 2014
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Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Revision Name : soc
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Revision Name : soc
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Top-level Entity Name : soc
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Top-level Entity Name : soc
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Family : Cyclone IV E
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Family : Cyclone IV E
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Device : EP4CE115F29C7
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Device : EP4CE115F29C7
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Timing Models : Final
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Timing Models : Final
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Total logic elements : 91,256 / 114,480 ( 80 % )
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Total logic elements : 91,256 / 114,480 ( 80 % )
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Total combinational functions : 86,811 / 114,480 ( 76 % )
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Total combinational functions : 86,811 / 114,480 ( 76 % )
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Dedicated logic registers : 26,746 / 114,480 ( 23 % )
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Dedicated logic registers : 26,746 / 114,480 ( 23 % )
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Total registers : 26865
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Total registers : 26865
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Total pins : 108 / 529 ( 20 % )
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Total pins : 108 / 529 ( 20 % )
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Total virtual pins : 0
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Total virtual pins : 0
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Total memory bits : 2,993,408 / 3,981,312 ( 75 % )
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Total memory bits : 2,993,408 / 3,981,312 ( 75 % )
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Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % )
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Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % )
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Total PLLs : 1 / 4 ( 25 % )
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Total PLLs : 1 / 4 ( 25 % )
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```
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```
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The maximum frequency is 39 MHz. The project uses a 30 MHz clock.
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The maximum frequency is 39 MHz. The project uses a 30 MHz clock.
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### Running software
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### Running software
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The ao486 successfuly runs the following software:
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The ao486 successfuly runs the following software:
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- Microsoft MS-DOS version 6.22,
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- Microsoft MS-DOS version 6.22,
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- Microsoft Windows for Workgroups 3.11,
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- Microsoft Windows for Workgroups 3.11,
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- Microsoft Windows 95,
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- Microsoft Windows 95,
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- Linux 3.13.1.
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- Linux 3.13.1.
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### BIOS
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### BIOS
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The ao486 project uses the BIOS from the Bochs project
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The ao486 project uses the BIOS from the Bochs project
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(http://bochs.sourceforge.net, version 2.6.2). Some minor changes
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(http://bochs.sourceforge.net, version 2.6.2). Some minor changes
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were required to support the hard drive.
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were required to support the hard drive.
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The VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios,
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The VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios,
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version 0.7a). No changes were required. The VGA model does not have VBE
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version 0.7a). No changes were required. The VGA model does not have VBE
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extensions, so the extensions were disabled.
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extensions, so the extensions were disabled.
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### NIOS2 controller
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### NIOS2 controller
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The ao486 SoC uses a Altera NIOS2 processor for managing all components and
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The ao486 SoC uses a Altera NIOS2 processor for managing all components and
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displaying the contents of the On Screen Display.
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displaying the contents of the On Screen Display.
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The OSD allows the user to insert and remove floppy disks.
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The OSD allows the user to insert and remove floppy disks.
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### License
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### License
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All files in the following directories:
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All files in the following directories:
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- rtl,
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- rtl,
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- ao486_tool,
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- ao486_tool,
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- sim
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- sim
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are licensed under the BSD license:
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are licensed under the BSD license:
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All files in the following directories:
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All files in the following directories:
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- bochs486,
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- bochs486,
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- bochsDevs
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- bochsDevs
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are taken from the Bochs Project and are licensed under the LGPL license.
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are taken from the Bochs Project and are licensed under the LGPL license.
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The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.
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The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.
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The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.
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The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.
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The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios
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The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios
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project.
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project.
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### Compiling
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### Compiling
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To compile the SoC, which contains the NIOS II microcontroller, Altera Quartus II software is required.
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To compile the SoC, which contains the NIOS II microcontroller, Altera Quartus II software is required.
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The Verilog components of the SoC, in particular the ao486 processor, should be possible to compile
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The Verilog components of the SoC, in particular the ao486 processor, should be possible to compile
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in any Verilog compiler. Currently synthesis project files are prepared only for Altera Quartus II.
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in any Verilog compiler. Currently synthesis project files are prepared only for Altera Quartus II.
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NOTE: In the current version some synthesis project files -- especially the paths in those files, could be
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NOTE: In the current version some synthesis project files -- especially the paths in those files, could be
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broken.
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broken.
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#### ao486 processor
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#### ao486 processor
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To compile the ao486 processor load the project file from syn/components/ao486/ao486.qpf.
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To compile the ao486 processor load the project file from syn/components/ao486/ao486.qpf.
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#### SoC
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#### SoC
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To compile the ao486 SoC load the project file from syn/soc/soc.qpf.
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To compile the ao486 SoC load the project file from syn/soc/soc.qpf.
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Before compiling in Altera Quartus II, the Qsys system must be generated.
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#### BIOS
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#### BIOS
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To compile the BIOS do the following:
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To compile the BIOS do the following:
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- extract the bochs-2.6.2 source archive,
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- extract the bochs-2.6.2 source archive,
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- apply the patch from the directory bios/bochs-2.6.2 by running in the extracted directory:
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- apply the patch from the directory bios/bochs-2.6.2 by running in the extracted directory:
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patch -p1 < (path to patch file)
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patch -p1 < (path to patch file)
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- run ./configure in bochs
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- run ./configure in bochs
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- run make in bochs
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- run make in bochs
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- cd bios
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- cd bios
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- make
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- make
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- the binary file BIOS-bochs-legacy works with ao486 SoC.
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- the binary file BIOS-bochs-legacy works with ao486 SoC.
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#### VGABIOS
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#### VGABIOS
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To compile the VGABIOS do the following:
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To compile the VGABIOS do the following:
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- extract the vgabios-0.7a source archive,
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- extract the vgabios-0.7a source archive,
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- apply the patch form the directory bios/vgabios-0.7a by running in the extracted directory:
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- apply the patch form the directory bios/vgabios-0.7a by running in the extracted directory:
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patch -p1 < (path to patch file)
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patch -p1 < (path to patch file)
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- run make in vgabios,
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- run make in vgabios,
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- the binary file VGABIOS-lgpl-latest.bin works with ao486 SoC.
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- the binary file VGABIOS-lgpl-latest.bin works with ao486 SoC.
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### Running the SoC on Terasic DE2-115
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### Running the SoC on Terasic DE2-115
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- compile the soc Altera Quartus II project in syn/soc/soc.qpf
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- compile the soc Altera Quartus II project in syn/soc/soc.qpf
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- compile the firmware for the NIOS II by:
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- compile the firmware for the NIOS II by:
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- opening the Nios II Software Build Tools for Eclipse,
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- opening the Nios II Software Build Tools for Eclipse,
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- creating a workspace in the directory syn/soc/firmware,
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- creating a workspace in the directory syn/soc/firmware,
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- importing the two projects 'exe' and 'exe_bsp',
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- importing the two projects 'exe' and 'exe_bsp',
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- genrating BSP on the 'exe_bsp' project,
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- genrating BSP on the 'exe_bsp' project,
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- compiling the 'exe' project.
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- compiling the 'exe' project.
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- compile the BIOS and copy the binary to the directory sd/bios
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- compile the BIOS and copy the binary to the directory sd/bios,
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- compile the VGABIOS and copy the binary to the directory sd/vgabios
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- compile the VGABIOS and copy the binary to the directory sd/vgabios,
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- compile the ao486_tool by running 'ant jar' in the directory ao486_tool
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- compile the ao486_tool by running 'ant jar' in the directory ao486_tool,
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- edit the files in the directory sd/hdd. They contain the position of the virtual hard disk located on
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- edit the files in the directory sd/hdd. They contain the position of the virtual hard disk located on
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the SD card. The start entry must be a multiplicity of 512. The values are in bytes from the begining
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the SD card. The start entry must be a multiplicity of 512. The values are in bytes from the begining
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of the SD card,
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of the SD card,
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- run 'java -cp ./dist/ao486_tool.jar ao486.SDGenerator' in the directory ao486_tool,
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- run 'java -cp ./dist/ao486_tool.jar ao486.SDGenerator' in the directory ao486_tool,
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- copy the file ao486_tool/sd.dat to the first sectors of the SD card by using 'dd if=sd.dat of=/dev/sdXXX'.
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- copy the file ao486_tool/sd.dat to the first sectors of the SD card by using 'dd if=sd.dat of=/dev/sdXXX'.
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- insert the SD card to the Terasic DE2-115 board,
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- program the FPGA using the SOF file,
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- program the FPGA using the SOF file,
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- load and run the firmware of the NIOS II controller,
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- load and run the firmware of the NIOS II controller,
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- select the BIOS file on the On Screen Display by using KEY0 for down, KEY1 for up and KEY2 for select,
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- select the BIOS file on the On Screen Display by using KEY0 for down, KEY1 for up and KEY2 for select,
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- select the VGABIOS file on the OSD,
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- select the VGABIOS file on the OSD,
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- select the hard drive on the OSD,
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- select the hard drive on the OSD,
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- select the floppy on the OSD. Use the KEYs to select the floppy image. Use KEY3 to cancel.
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- select the floppy on the OSD. Use the KEYs to select the floppy image. Use KEY3 to cancel.
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- after selecting the floppy or pressing cancel, ao486 boots,
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- after selecting the floppy or pressing cancel, ao486 boots,
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- to activate the OSD press KEY2.
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- to activate the OSD press KEY2.
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