//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// AES CORE BLOCK
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//// AES CORE BLOCK
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////
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////
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////
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////
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////
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////
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//// This file is part of the APB to I2C project
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//// This file is part of the APB to AES128 project
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////
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////
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//// http://www.opencores.org/cores/apbi2c/
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//// http://www.opencores.org/cores/apbtoaes128/
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////
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////
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////
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////
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////
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////
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//// Description
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//// Description
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////
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////
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//// Implementation of APB IP core according to
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//// Implementation of APB IP core according to
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////
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////
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//// aes128_spec IP core specification document.
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//// aes128_spec IP core specification document.
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////
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////
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////
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Julio Cesar
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//// Julio Cesar
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////
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////
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/////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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////
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////
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////
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//// This source file may be used and distributed without
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//// This source file may be used and distributed without
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////
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////
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//// restriction provided that this copyright statement is not
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//// restriction provided that this copyright statement is not
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////
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////
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//// removed from the file and that any derivative work contains
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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//// the original copyright notice and the associated disclaimer.
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////
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////
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////
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////
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//// This source file is free software; you can redistribute it
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//// This source file is free software; you can redistribute it
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////
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////
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//// and/or modify it under the terms of the GNU Lesser General
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//// and/or modify it under the terms of the GNU Lesser General
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////
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////
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//// Public License as published by the Free Software Foundation;
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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//// either version 2.1 of the License, or (at your option) any
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////
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////
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//// later version.
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//// later version.
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////
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////
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////
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////
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////
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////
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//// This source is distributed in the hope that it will be
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//// This source is distributed in the hope that it will be
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////
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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//// details.
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////
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////
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////
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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//// You should have received a copy of the GNU Lesser General
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////
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////
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//// Public License along with this source; if not, download it
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//// Public License along with this source; if not, download it
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////
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////
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//// from http://www.opencores.org/lgpl.shtml
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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////
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////
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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module aes_core
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module aes_core
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(
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(
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//OUTPUTS
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//OUTPUTS
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output [31:0] col_out,
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output [31:0] col_out,
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output [31:0] key_out,
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output [31:0] key_out,
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output [31:0] iv_out,
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output [31:0] iv_out,
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output end_aes,
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output end_aes,
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//INPUTS
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//INPUTS
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input [31:0] bus_in,
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input [31:0] bus_in,
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input [ 3:0] iv_en,
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input [ 3:0] iv_en,
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input [ 3:0] iv_sel_rd,
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input [ 3:0] iv_sel_rd,
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input [ 3:0] key_en,
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input [ 3:0] key_en,
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input [ 1:0] key_sel_rd,
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input [ 1:0] key_sel_rd,
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input [ 1:0] data_type,
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input [ 1:0] data_type,
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input [ 1:0] addr,
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input [ 1:0] addr,
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input [ 1:0] op_mode,
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input [ 1:0] op_mode,
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input [ 1:0] aes_mode,
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input [ 1:0] aes_mode,
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input start,
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input start,
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input disable_core,
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input disable_core,
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input write_en,
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input write_en,
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input read_en,
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input read_en,
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input first_block,
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input first_block,
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input rst_n,
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input rst_n,
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input clk
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input clk
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);
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);
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wire [ 1:0] rk_sel;
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wire [ 1:0] rk_sel;
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wire [ 1:0] key_out_sel;
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wire [ 1:0] key_out_sel;
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wire [ 3:0] round;
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wire [ 3:0] round;
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wire [ 2:0] sbox_sel;
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wire [ 2:0] sbox_sel;
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wire [ 3:0] col_en_host;
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wire [ 3:0] col_en_host;
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wire [ 3:0] iv_en_host;
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wire [ 3:0] iv_en_host;
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wire [ 3:0] col_en_cnt_unit;
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wire [ 3:0] col_en_cnt_unit;
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wire [ 3:0] key_en_host;
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wire [ 3:0] key_en_host;
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wire [ 3:0] key_en_cnt_unit;
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wire [ 3:0] key_en_cnt_unit;
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wire [ 1:0] col_sel;
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wire [ 1:0] col_sel;
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wire key_sel;
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wire key_sel;
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wire bypass_rk;
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wire bypass_rk;
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wire bypass_key_en;
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wire bypass_key_en;
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wire last_round;
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wire last_round;
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wire iv_cnt_en;
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wire iv_cnt_en;
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wire iv_cnt_sel;
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wire iv_cnt_sel;
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wire mode_ctr;
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wire mode_ctr;
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wire mode_cbc;
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wire mode_cbc;
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wire key_init;
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wire key_init;
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wire key_gen;
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wire key_gen;
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wire [1:0] col_addr_host;
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wire [1:0] col_addr_host;
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assign col_en_host = (4'b0001 << addr) & {4{write_en}};
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assign col_en_host = (4'b0001 << addr) & {4{write_en}};
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assign col_addr_host = addr & {2{read_en}};
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assign col_addr_host = addr & {2{read_en}};
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assign iv_en_host = iv_en;
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assign iv_en_host = iv_en;
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assign key_en_host = key_en;
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assign key_en_host = key_en;
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datapath AES_CORE_DATAPATH
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datapath AES_CORE_DATAPATH
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(
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(
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.col_bus ( col_out ),
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.col_bus ( col_out ),
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.key_bus ( key_out ),
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.key_bus ( key_out ),
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.iv_bus ( iv_out ),
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.iv_bus ( iv_out ),
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.bus_in ( bus_in ),
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.bus_in ( bus_in ),
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.end_aes ( end_aes ),
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.end_aes ( end_aes ),
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.data_type ( data_type ),
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.data_type ( data_type ),
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.rk_sel ( rk_sel ),
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.rk_sel ( rk_sel ),
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.key_out_sel ( key_out_sel ),
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.key_out_sel ( key_out_sel ),
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.round ( round ),
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.round ( round ),
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.sbox_sel ( sbox_sel ),
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.sbox_sel ( sbox_sel ),
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.iv_en ( iv_en_host ),
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.iv_en ( iv_en_host ),
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.iv_sel_rd ( iv_sel_rd ),
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.iv_sel_rd ( iv_sel_rd ),
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.col_en_host ( col_en_host ),
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.col_en_host ( col_en_host ),
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.col_en_cnt_unit ( col_en_cnt_unit ),
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.col_en_cnt_unit ( col_en_cnt_unit ),
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.key_host_en ( key_en_host ),
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.key_host_en ( key_en_host ),
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.key_en ( key_en_cnt_unit ),
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.key_en ( key_en_cnt_unit ),
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.key_sel_rd ( key_sel_rd ),
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.key_sel_rd ( key_sel_rd ),
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.col_sel_host ( col_addr_host ),
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.col_sel_host ( col_addr_host ),
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.col_sel ( col_sel ),
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.col_sel ( col_sel ),
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.key_sel ( key_sel ),
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.key_sel ( key_sel ),
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.bypass_rk ( bypass_rk ),
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.bypass_rk ( bypass_rk ),
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.bypass_key_en ( bypass_key_en ),
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.bypass_key_en ( bypass_key_en ),
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.first_block ( first_block ),
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.first_block ( first_block ),
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.last_round ( last_round ),
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.last_round ( last_round ),
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.iv_cnt_en ( iv_cnt_en ),
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.iv_cnt_en ( iv_cnt_en ),
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.iv_cnt_sel ( iv_cnt_sel ),
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.iv_cnt_sel ( iv_cnt_sel ),
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.enc_dec ( enc_dec ),
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.enc_dec ( enc_dec ),
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.mode_ctr ( mode_ctr ),
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.mode_ctr ( mode_ctr ),
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.mode_cbc ( mode_cbc ),
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.mode_cbc ( mode_cbc ),
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.key_init ( key_init ),
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.key_init ( key_init ),
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.key_gen ( key_gen ),
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.key_gen ( key_gen ),
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.key_derivation_en ( key_derivation_en ),
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.key_derivation_en ( key_derivation_en ),
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.end_comp ( end_comp ),
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.end_comp ( end_comp ),
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.rst_n ( rst_n ),
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.rst_n ( rst_n ),
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.clk ( clk )
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.clk ( clk )
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);
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);
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control_unit AES_CORE_CONTROL_UNIT
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control_unit AES_CORE_CONTROL_UNIT
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(
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(
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.end_comp ( end_comp ),
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.end_comp ( end_comp ),
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.sbox_sel ( sbox_sel ),
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.sbox_sel ( sbox_sel ),
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.rk_sel ( rk_sel ),
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.rk_sel ( rk_sel ),
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.key_out_sel ( key_out_sel ),
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.key_out_sel ( key_out_sel ),
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.col_sel ( col_sel ),
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.col_sel ( col_sel ),
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.key_en ( key_en_cnt_unit ),
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.key_en ( key_en_cnt_unit ),
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.col_en ( col_en_cnt_unit ),
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.col_en ( col_en_cnt_unit ),
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.round ( round ),
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.round ( round ),
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.bypass_rk ( bypass_rk ),
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.bypass_rk ( bypass_rk ),
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.bypass_key_en ( bypass_key_en ),
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.bypass_key_en ( bypass_key_en ),
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.key_sel ( key_sel ),
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.key_sel ( key_sel ),
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.last_round ( last_round ),
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.last_round ( last_round ),
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.iv_cnt_en ( iv_cnt_en ),
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.iv_cnt_en ( iv_cnt_en ),
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.iv_cnt_sel ( iv_cnt_sel ),
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.iv_cnt_sel ( iv_cnt_sel ),
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.mode_ctr ( mode_ctr ),
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.mode_ctr ( mode_ctr ),
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.mode_cbc ( mode_cbc ),
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.mode_cbc ( mode_cbc ),
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.key_init ( key_init ),
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.key_init ( key_init ),
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.encrypt_decrypt ( enc_dec ),
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.encrypt_decrypt ( enc_dec ),
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.key_gen ( key_gen ),
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.key_gen ( key_gen ),
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.operation_mode ( op_mode ),
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.operation_mode ( op_mode ),
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.aes_mode ( aes_mode ),
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.aes_mode ( aes_mode ),
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.start ( start ),
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.start ( start ),
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.key_derivation_en ( key_derivation_en ),
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.key_derivation_en ( key_derivation_en ),
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.disable_core ( disable_core ),
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.disable_core ( disable_core ),
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.clk ( clk ),
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.clk ( clk ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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endmodule
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endmodule
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