//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// AES CORE BLOCK
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//// AES CORE BLOCK
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////
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////
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////
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////
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////
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////
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//// This file is part of the APB to I2C project
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//// This file is part of the APB to AES128 project
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////
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////
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//// http://www.opencores.org/cores/apbi2c/
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//// http://www.opencores.org/cores/apbtoaes128/
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////
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////
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////
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////
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////
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////
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//// Description
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//// Description
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////
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////
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//// Implementation of APB IP core according to
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//// Implementation of APB IP core according to
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////
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////
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//// aes128_spec IP core specification document.
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//// aes128_spec IP core specification document.
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////
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////
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////
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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//// Julio Cesar
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//// Julio Cesar
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////
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////
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/////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////
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////
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////
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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////
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////
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////
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//// This source file may be used and distributed without
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//// This source file may be used and distributed without
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////
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////
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//// restriction provided that this copyright statement is not
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//// restriction provided that this copyright statement is not
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////
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////
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//// removed from the file and that any derivative work contains
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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//// the original copyright notice and the associated disclaimer.
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////
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////
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////
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////
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//// This source file is free software; you can redistribute it
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//// This source file is free software; you can redistribute it
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////
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////
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//// and/or modify it under the terms of the GNU Lesser General
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//// and/or modify it under the terms of the GNU Lesser General
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////
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////
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//// Public License as published by the Free Software Foundation;
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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//// either version 2.1 of the License, or (at your option) any
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////
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////
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//// later version.
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//// later version.
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////
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////
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////
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////
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////
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////
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//// This source is distributed in the hope that it will be
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//// This source is distributed in the hope that it will be
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////
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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//// details.
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////
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////
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////
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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//// You should have received a copy of the GNU Lesser General
|
////
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////
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//// Public License along with this source; if not, download it
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//// Public License along with this source; if not, download it
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////
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////
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//// from http://www.opencores.org/lgpl.shtml
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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////
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////
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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module shift_rows
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module shift_rows
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(
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(
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//OUTPUTS
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//OUTPUTS
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output [127 : 0] data_out_enc, // Result after Shift Rows operation - enc
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output [127 : 0] data_out_enc, // Result after Shift Rows operation - enc
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output [127 : 0] data_out_dec, // Result after Shift Rows operation - dec
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output [127 : 0] data_out_dec, // Result after Shift Rows operation - dec
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//INPUTS
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//INPUTS
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input [127 : 0] data_in // Input Bus
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input [127 : 0] data_in // Input Bus
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);
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);
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localparam BUS_WIDTH = 128; // Bus Width
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localparam BUS_WIDTH = 128; // Bus Width
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localparam ST_WORD = 8; // Data Size of word in State MAtrix
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localparam ST_WORD = 8; // Data Size of word in State MAtrix
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localparam ST_LINE = 4; // Number of Lines of State Matrix
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localparam ST_LINE = 4; // Number of Lines of State Matrix
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localparam ST_COL = 4; // Number of Columns of State Matrix
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localparam ST_COL = 4; // Number of Columns of State Matrix
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|
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wire [ST_WORD - 1 : 0] state[0 : ST_LINE - 1][0 : ST_COL - 1];
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wire [ST_WORD - 1 : 0] state[0 : ST_LINE - 1][0 : ST_COL - 1];
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wire [ST_WORD - 1 : 0] state_sft_l[0 : ST_LINE - 1][0 : ST_COL - 1];
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wire [ST_WORD - 1 : 0] state_sft_l[0 : ST_LINE - 1][0 : ST_COL - 1];
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wire [ST_WORD - 1 : 0] state_sft_r[0 : ST_LINE - 1][0 : ST_COL - 1];
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wire [ST_WORD - 1 : 0] state_sft_r[0 : ST_LINE - 1][0 : ST_COL - 1];
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//=====================================================================================
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//=====================================================================================
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// State Matrix generation
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// State Matrix generation
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//=====================================================================================
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//=====================================================================================
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generate
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generate
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genvar l,c;
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genvar l,c;
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for(l = 0; l < ST_LINE; l = l + 1)
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for(l = 0; l < ST_LINE; l = l + 1)
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for(c = 0; c < ST_COL; c = c + 1)
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for(c = 0; c < ST_COL; c = c + 1)
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assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
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assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
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endgenerate
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endgenerate
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//=====================================================================================
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//=====================================================================================
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// Shift Row operation
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// Shift Row operation
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//=====================================================================================
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//=====================================================================================
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generate
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generate
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genvar l1,c1;
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genvar l1,c1;
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for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
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for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
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for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
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for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
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begin
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begin
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assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
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assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
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assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
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assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
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end
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end
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endgenerate
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endgenerate
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//=====================================================================================
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//=====================================================================================
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// State Matrix to Bus Output Transformation
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// State Matrix to Bus Output Transformation
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//=====================================================================================
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//=====================================================================================
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generate
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generate
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genvar l2,c2;
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genvar l2,c2;
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for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
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for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
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for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
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for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
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begin
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begin
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assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
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assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
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assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
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assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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