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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [adder_tree.vhd] - Diff between revs 9 and 11

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Rev 9 Rev 11
Line 44... Line 44...
   );
   );
end adder_tree;
end adder_tree;
 
 
architecture Behavioral of adder_tree is
architecture Behavioral of adder_tree is
 
 
 
 
 
 
 
   component adder_tree is
 
      generic
 
      (
 
         NumIn   : integer := 9;  -- Number of inputs
 
         Nbit    : integer := 12  -- Bit width of the input data
 
      );
 
 
 
      port
 
      (
 
         -- Input ports
 
         reset    : in  std_logic;
 
         clk      : in  std_logic;
 
         en       : in  std_logic; -- Enable
 
         inputs   : in  std_logic_vector((Nbit*NumIn)-1 downto 0); -- Input data
 
 
 
         -- Output ports
 
         en_out   : out std_logic; -- Output enable (output data validation)
 
         output   : out std_logic_vector(Nbit-1 downto 0) -- Output of the tree adder
 
      );
 
   end component;
 
 
   constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer
   constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer
 
 
   signal next_en : std_logic := '0'; -- Next adder tree layer enable
   signal next_en : std_logic := '0'; -- Next adder tree layer enable
   signal res : std_logic_vector((Nbit*((NumIn2)+(NumIn mod 2)))-1 downto 0); -- Partial results
   signal res : std_logic_vector((Nbit*((NumIn2)+(NumIn mod 2)))-1 downto 0); -- Partial results
 
 
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   end process;
   end process;
 
 
recursion:
recursion:
   if (NumIn > 2) generate
   if (NumIn > 2) generate
 
 
      sub_adder_tree: entity work.adder_tree
      sub_adder_tree: adder_tree
         generic map
         generic map
         (
         (
            NumIn => (NumIn2)+(NumIn mod 2),
            NumIn => (NumIn2)+(NumIn mod 2),
            Nbit  => Nbit
            Nbit  => Nbit
         )
         )

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