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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [layerPS_top.vhd] - Diff between revs 9 and 10

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Rev 9 Rev 10
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----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
 
 
library work;
 
use work.wb_init.all; -- initialization package, comment out when not used
use work.wb_init.all; -- initialization package, comment out when not used
 
 
-- Deprecated XPS library:
-- Deprecated XPS library:
--library proc_common_v3_00_a;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
 
 
entity layerPS_top is
entity layerPS_top is
 
 
   generic
   generic
   (
   (
      WBinit  : boolean := false;
      NumN    : natural := 64;  ------- Number of neurons of the layer
      LNum    : natural := 0;   ------- layer number (needed for initialization)
      NumIn   : natural := 8;   ------- Number of inputs of each neuron
      NumN    : natural := 34;  ------- Number of neurons of the layer
      NbitIn  : natural := 12;  ------- Bit width of the input data
      NumIn   : natural := 27;   ------- Number of inputs of each neuron
      NbitW   : natural := 8;   ------- Bit width of weights and biases
      NbitIn  : natural := 8;  ------- Bit width of the input data
 
      NbitW   : natural := 1;   ------- Bit width of weights and biases
 
      NbitOut : natural := 8;   ------- Bit width of the output data
      NbitOut : natural := 8;   ------- Bit width of the output data
      lra_l   : natural := 11;  ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
      lra_l   : natural := 10;  ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
      wra_l   : natural := 5;   ------- Weight RAM address length. It should value log2(NumIn)
      wra_l   : natural := 3;   ------- Weight RAM address length. It should value log2(NumIn)
      bra_l   : natural := 6;   ------- Bias RAM address length. It should value log2(NumN)
      bra_l   : natural := 6;   ------- Bias RAM address length. It should value log2(NumN)
      LSbit   : natural := 6    ------- Less significant bit of the outputs
      LSbit   : natural := 4;   ------- Less significant bit of the outputs
 
      WBinit  : boolean := false;
 
      LNum    : natural := 0    ------- layer number (needed for initialization)
   );
   );
 
 
   port
   port
   (
   (
      -- Input ports
      -- Input ports
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end layerPS_top;
end layerPS_top;
 
 
architecture Behavioral of layerPS_top is
architecture Behavioral of layerPS_top is
 
 
 
   --type ramd_type is array (pad_power2(NumN)-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces -- pad_power2() only for simulation
 
   --type layer_ram is array (pad_power2(NumIn)-1 downto 0) of ramd_type;
   type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
   type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
   type layer_ram is array (NumIn-1 downto 0) of ramd_type;
   type layer_ram is array (NumIn-1 downto 0) of ramd_type;
   type outm_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
   type outm_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
 
 
   function fw_init(LNum : natural) return layer_ram is
   function fw_init(LNum : natural) return layer_ram is

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