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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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use work.wb_init.all; -- initialization package, comment out when not used
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-- Deprecated XPS library:
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-- Deprecated XPS library:
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--library proc_common_v3_00_a;
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--library proc_common_v3_00_a;
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--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
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--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
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entity layerPS_top is
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entity layerPS_top is
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generic
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generic
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(
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(
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NumN : natural := 64; ------- Number of neurons of the layer
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WBinit : boolean := false;
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NumIn : natural := 8; ------- Number of inputs of each neuron
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LNum : natural := 0; ------- layer number (needed for initialization)
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NbitIn : natural := 12; ------- Bit width of the input data
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NumN : natural := 34; ------- Number of neurons of the layer
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NbitW : natural := 8; ------- Bit width of weights and biases
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NumIn : natural := 27; ------- Number of inputs of each neuron
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NbitIn : natural := 8; ------- Bit width of the input data
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NbitW : natural := 1; ------- Bit width of weights and biases
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NbitOut : natural := 8; ------- Bit width of the output data
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NbitOut : natural := 8; ------- Bit width of the output data
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lra_l : natural := 10; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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lra_l : natural := 11; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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wra_l : natural := 3; ------- Weight RAM address length. It should value log2(NumIn)
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wra_l : natural := 5; ------- Weight RAM address length. It should value log2(NumIn)
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bra_l : natural := 6; ------- Bias RAM address length. It should value log2(NumN)
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bra_l : natural := 6; ------- Bias RAM address length. It should value log2(NumN)
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LSbit : natural := 4 ------- Less significant bit of the outputs
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LSbit : natural := 6 ------- Less significant bit of the outputs
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);
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);
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port
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port
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(
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(
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-- Input ports
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-- Input ports
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end layerPS_top;
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end layerPS_top;
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architecture Behavioral of layerPS_top is
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architecture Behavioral of layerPS_top is
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--type ramd_type is array (pad_power2(NumN)-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces -- pad_power2() only for simulation
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--type layer_ram is array (pad_power2(NumIn)-1 downto 0) of ramd_type;
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type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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type layer_ram is array (NumIn-1 downto 0) of ramd_type;
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type layer_ram is array (NumIn-1 downto 0) of ramd_type;
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type outm_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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type outm_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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signal lram : layer_ram; -- Layer RAM. One RAM per input. It stores the weights
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function fw_init(LNum : natural) return layer_ram is
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signal breg : ramd_type; -- Bias RAM. They can be RAM because they are not accessed simultaneously
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variable tmp_arr : layer_ram := (others =>(others => (others => '0')));
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begin
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if WBinit = true then
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for i in 0 to NumIn-1 loop
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for j in 0 to NumN-1 loop
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tmp_arr(i)(j) := w_init(LNum)(i)(j);
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end loop;
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end loop;
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end if;
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return tmp_arr ;
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end fw_init;
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function fb_init(LNum : natural) return ramd_type is
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variable tmp_arr : ramd_type := (others => (others => '0')) ;
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begin
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if WBinit = true then
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for i in 0 to NumN-1 loop
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tmp_arr(i) := b_init(LNum)(i);
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end loop;
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end if;
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return tmp_arr;
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end fb_init;
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--function fb_init(LNum : natural) return ramd_type is
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--begin
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-- return ramd_type(b_init(LNum));
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--end fb_init;
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signal lram : layer_ram := fw_init(LNum); -- Layer RAM. One RAM per input. It stores the weights
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signal breg : ramd_type := fb_init(LNum); -- Bias RAM. They can be RAM because they are not accessed simultaneously
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signal outm : outm_type; -- RAM outputs to be multiplexed into rdata
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signal outm : outm_type; -- RAM outputs to be multiplexed into rdata
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signal m_sel : std_logic_vector(NumIn-1 downto 0); --------- RAM select
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signal m_sel : std_logic_vector(NumIn-1 downto 0); --------- RAM select
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signal Wyb : std_logic_vector((NbitW*NumIn)-1 downto 0); -- Weight vectors
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signal Wyb : std_logic_vector((NbitW*NumIn)-1 downto 0); -- Weight vectors
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signal bias : std_logic_vector(NbitW-1 downto 0); -------- Bias
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signal bias : std_logic_vector(NbitW-1 downto 0); -------- Bias
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signal Nouts : std_logic_vector(NbitOut-1 downto 0); ------ Outputs from neurons
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signal Nouts : std_logic_vector(NbitOut-1 downto 0); ------ Outputs from neurons
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signal uaddr : unsigned(lra_l-1 downto 0); -- Unsigned address of weight and bias memories
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signal uaddr : unsigned(lra_l-1 downto 0); -- Unsigned address of weight and bias memories
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-- Señales de control
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-- Señales de control
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signal cont : integer range 0 to NumN-1; -- Neuron counter
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signal cont : integer range 0 to NumN-1; -- Neuron counter
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signal cntb : integer range 0 to NumN-1; -- Delayed counter for biases
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signal cntb : integer range 0 to NumN-1; -- Delayed counter for biases
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signal st : bit; ------- State
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signal st : bit; ------- State
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signal en1 : std_logic; -- First step enable
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signal en1 : std_logic; -- First step enable
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signal en2 : std_logic; -- Second stage enable
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signal en2 : std_logic; -- Second stage enable
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signal en3 : std_logic; -- Shift register enable
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signal en3 : std_logic; -- Shift register enable
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signal en_out : std_logic;
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signal en_out : std_logic;
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signal input_aux1 : std_logic_vector((NbitIn*NumIn)-1 downto 0);
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signal input_aux2 : std_logic_vector((NbitIn*NumIn)-1 downto 0);
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signal input_aux3 : std_logic_vector((NbitIn*NumIn)-1 downto 0);
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begin
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begin
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layerPS_inst: entity work.layerPS
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layerPS_inst: entity work.layerPS
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generic map
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generic map
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(
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(
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reset => reset,
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reset => reset,
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clk => clk,
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clk => clk,
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en => en1,
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en => en1,
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en2 => en2,
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en2 => en2,
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en_r => en3,
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en_r => en3,
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inputs => inputs,
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inputs => input_aux2,
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Wyb => Wyb,
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Wyb => Wyb,
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bias => bias,
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bias => bias,
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-- Output ports
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-- Output ports
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en_out => en_out,
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en_out => en_out,
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st <= '0';
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st <= '0';
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en1 <= '0';
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en1 <= '0';
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en2 <= '0';
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en2 <= '0';
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run_out <= '0';
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run_out <= '0';
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else
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else
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input_aux1 <= inputs;
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input_aux2 <= input_aux1;
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--input_aux3 <=input_aux3 input_aux2;
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cntb <= cont; -- Bias counter is delayed to assure correctness of pipeline data
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cntb <= cont; -- Bias counter is delayed to assure correctness of pipeline data
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case st is
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case st is
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when '0' =>
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when '0' =>
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en1 <= '0'; -- en1 is delayed 1 cycle in order to insert a register for Wyb
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en1 <= '0'; -- en1 is delayed 1 cycle in order to insert a register for Wyb
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case run_in is
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case run_in is
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when '0' => st <= '0';
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when '0' => st <= '0';
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when others => st <= '0';
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when others => st <= '0';
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end case;
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end case;
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when '1' =>
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when '1' =>
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en1 <= '1'; -- en1 is delayed 1 cycle in order to insert a register for Wyb
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en1 <= '1'; -- en1 is delayed 1 cycle in order to insert a register for Wyb
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case cont is
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if cont = NumN-1 then
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when (NumN-1) =>
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cont <= 0;
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cont <= 0;
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st <= '0';
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st <= '0';
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when others =>
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else
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cont <= cont +1;
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cont <= cont +1;
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end case;
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end if;
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end case;
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end case;
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en2 <= en1;
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en2 <= en1;
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run_out <= en3; -- It lasts for 1 cycle, just after the output enable of the layer (when all outputs have just updated)
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run_out <= en3; -- It lasts for 1 cycle, just after the output enable of the layer (when all outputs have just updated)
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