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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [layerSP_top.vhd] - Diff between revs 8 and 10

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Rev 8 Rev 10
Line 31... Line 31...
 
 
entity layerSP_top is
entity layerSP_top is
 
 
   generic
   generic
   (
   (
      WBinit  : boolean := false;
      NumN    : natural := 8;   ------- Number of neurons of the layer
      LNum    : natural := 0;   ------- layer number (needed for initialization)
      NumIn   : natural := 64;  ------- Number of inputs of each neuron
      NumN    : natural := 34;   ------- Number of neurons of the layer
 
      NumIn   : natural := 27;  ------- Number of inputs of each neuron
 
      NbitIn  : natural := 8;   ------- Bit width of the input data
      NbitIn  : natural := 8;   ------- Bit width of the input data
      NbitW   : natural := 32;   ------- Bit width of weights and biases
      NbitW   : natural := 8;   ------- Bit width of weights and biases
      NbitOut : natural := 8;  ------- Bit width of the output data
      NbitOut : natural := 12;  ------- Bit width of the output data
      lra_l   : natural := 11;  ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
      lra_l   : natural := 10;  ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
      wra_l   : natural := 5;   ------- Weight RAM address length. It should value log2(NumIn)
      wra_l   : natural := 6;   ------- Weight RAM address length. It should value log2(NumIn)
      bra_l   : natural := 6;   ------- Bias RAM address length. It should value log2(NumN)
      bra_l   : natural := 3;   ------- Bias RAM address length. It should value log2(NumN)
      LSbit   : natural := 6    ------- Less significant bit of the outputs
      LSbit   : natural := 4;    ------- Less significant bit of the outputs
 
      WBinit  : boolean := false;
 
      LNum    : natural := 0   ------- layer number (needed for initialization)
 
 
   );
   );
 
 
   port
   port
   (
   (
      -- Input ports
      -- Input ports
Line 208... Line 209...
 
 
   -- Synchronous read including breg:
   -- Synchronous read including breg:
   process (clk)
   process (clk)
   begin
   begin
      if (clk'event and clk = '1') then
      if (clk'event and clk = '1') then
         --report "addr: " & integer'image(wra_l-1);
 
         --report "addr: " & integer'image(to_integer(uaddr(wra_l-1 downto 0))  );
 
         if (m_en = '1') then
         if (m_en = '1') then
            if (b_sel = '1') then
            if (b_sel = '1') then
               rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
               rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
            else -- Other RAM selected:
            else -- Other RAM selected:
               rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
               rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs

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