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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [layerSP_top.vhd] - Diff between revs 3 and 8

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----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
 
 
 
library work;
 
use work.wb_init.all; -- initialization package, comment out when not used
 
 
-- Deprecated XPS library:
-- Deprecated XPS library:
--library proc_common_v3_00_a;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
 
 
entity layerSP_top is
entity layerSP_top is
 
 
   generic
   generic
   (
   (
      NumN    : natural := 8;   ------- Number of neurons of the layer
      WBinit  : boolean := false;
      NumIn   : natural := 64;  ------- Number of inputs of each neuron
      LNum    : natural := 0;   ------- layer number (needed for initialization)
 
      NumN    : natural := 34;   ------- Number of neurons of the layer
 
      NumIn   : natural := 27;  ------- Number of inputs of each neuron
      NbitIn  : natural := 8;   ------- Bit width of the input data
      NbitIn  : natural := 8;   ------- Bit width of the input data
      NbitW   : natural := 8;   ------- Bit width of weights and biases
      NbitW   : natural := 32;   ------- Bit width of weights and biases
      NbitOut : natural := 12;  ------- Bit width of the output data
      NbitOut : natural := 8;  ------- Bit width of the output data
      lra_l   : natural := 10;  ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
      lra_l   : natural := 11;  ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
      wra_l   : natural := 6;   ------- Weight RAM address length. It should value log2(NumIn)
      wra_l   : natural := 5;   ------- Weight RAM address length. It should value log2(NumIn)
      bra_l   : natural := 3;   ------- Bias RAM address length. It should value log2(NumN)
      bra_l   : natural := 6;   ------- Bias RAM address length. It should value log2(NumN)
      LSbit   : natural := 4    ------- Less significant bit of the outputs
      LSbit   : natural := 6    ------- Less significant bit of the outputs
   );
   );
 
 
   port
   port
   (
   (
      -- Input ports
      -- Input ports
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end layerSP_top;
end layerSP_top;
 
 
architecture Behavioral of layerSP_top is
architecture Behavioral of layerSP_top is
 
 
   --type ramd_type is array (pad_power2(NumIn)-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
 
   --type layer_ram is array (pad_power2(NumN)-1 downto 0) of ramd_type;
 
   type ramd_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
   type ramd_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
   type layer_ram is array (NumN-1 downto 0) of ramd_type;
   type layer_ram is array (NumN-1 downto 0) of ramd_type;
   type outm_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
   type outm_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
 
 
   signal lram  : layer_ram; -- Layer RAM. One RAM per neuron. It stores the weights
 
   signal breg  : outm_type; -- Bias registers. They can not be RAM because they are accessed simultaneously
   function fw_init(LNum : natural) return layer_ram is
 
     variable tmp_arr : layer_ram := (others => (others => (others => '0'))) ;
 
   begin
 
      if WBinit = true then
 
          for i in 0 to NumIn-1 loop
 
             for j in 0 to NumN-1 loop
 
                tmp_arr(j)(i) := w_init(LNum)(i)(j);
 
             end loop;
 
          end loop;
 
      end if;
 
      return tmp_arr ;
 
   end fw_init;
 
 
 
   function fb_init(LNum : natural) return outm_type is
 
      variable tmp_arr : outm_type := (others => (others => '0')) ;
 
   begin
 
      if WBinit = true then
 
         for i in 0 to NumN-1 loop
 
           tmp_arr(i) := b_init(LNum)(i);
 
         end loop;
 
      end if;
 
      return tmp_arr;
 
   end fb_init;
 
 
 
 
 
 
 
   signal lram  : layer_ram := fw_init(LNum); -- Layer RAM. One RAM per neuron. It stores the weights
 
   signal breg  : outm_type := fb_init(LNum); -- Bias registers. They can not be RAM because they are accessed simultaneously
   signal outm  : outm_type; -- RAM outputs to be multiplexed into rdata
   signal outm  : outm_type; -- RAM outputs to be multiplexed into rdata
   signal m_sel : std_logic_vector(NumN-1 downto 0);     -------- RAM select
   signal m_sel : std_logic_vector(NumN-1 downto 0);     -------- RAM select
   signal Wyb   : std_logic_vector((NbitW*NumN)-1 downto 0);  --- Weight vectors
   signal Wyb   : std_logic_vector((NbitW*NumN)-1 downto 0);  --- Weight vectors
   signal bias  : std_logic_vector((NbitW*NumN)-1 downto 0);  --- Bias vector
   signal bias  : std_logic_vector((NbitW*NumN)-1 downto 0);  --- Bias vector
   signal Nouts : std_logic_vector((NbitOut*NumN)-1 downto 0); -- Outputs from neurons
   signal Nouts : std_logic_vector((NbitOut*NumN)-1 downto 0); -- Outputs from neurons
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            else
            else
               Wyb((NbitW*(i+1))-1 downto NbitW*i) <= lram(i)(cont);
               Wyb((NbitW*(i+1))-1 downto NbitW*i) <= lram(i)(cont);
            end if;
            end if;
         end if;
         end if;
      end process;
      end process;
      outm(i) <= lram(i)(to_integer(uaddr(wra_l-1 downto 0))); -- Read all RAM
      outm(i) <= lram(i)(to_integer(uaddr(wra_l-1 downto 0))) when (uaddr(wra_l-1 downto 0) <= NumIn-1) else
 
                 (others => '0')  ; -- Read all RAM
 
      -- In my case I have 27 inputs and 34 neurons in the first layer. When I address
 
      -- the 1 layer's inputs for the second neuron the layer which acccepts a 6 bit wide
 
      -- input address (layer 2) sees the ..1 00100 (34) number and interprets it as an input
 
      -- address (which goes only up to 33) hence the bound check failure 
 
      -- fix: I've changed the assignment to a conditional one to check if we are not
 
      -- trying to read a weight of an input higher than the number of this layer's inputs. 
   end generate;
   end generate;
 
 
   -- Synchronous read including breg:
   -- Synchronous read including breg:
   process (clk)
   process (clk)
   begin
   begin
      if (clk'event and clk = '1') then
      if (clk'event and clk = '1') then
 
         --report "addr: " & integer'image(wra_l-1);
 
         --report "addr: " & integer'image(to_integer(uaddr(wra_l-1 downto 0))  );
         if (m_en = '1') then
         if (m_en = '1') then
            if (b_sel = '1') then
            if (b_sel = '1') then
               rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
               rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
            else -- Other RAM selected:
            else -- Other RAM selected:
               rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
               rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
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                  cont <= 0; -- Restarts input counter
                  cont <= 0; -- Restarts input counter
                  aux2_en3 <= '1';
                  aux2_en3 <= '1';
               else
               else
                  cont <= cont +1;
                  cont <= cont +1;
               end if;
               end if;
 
            --elsif (cont = NumIn-1) then -- for layers with more that
 
            --   cont <= 0;               -- 1 neuron uncommenting this
 
            --   aux2_en3 <= '1';         -- solved a problem with cont resetting
            end if;
            end if;
            en2 <= en1;
            en2 <= en1;
            if (cont = 0 and run_in = '1') then
            if (cont = 0 and run_in = '1') then
               aux_a0 <= '1'; -- At the count beginning
               aux_a0 <= '1'; -- At the count beginning
            else
            else

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