library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.layers_pkg.all;
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use work.layers_pkg.all;
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package support_pkg is
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package support_pkg is
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-- generic constants:
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-- generic constants:
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constant NbitIn : natural := 12;
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constant NbitIn : natural := 12;
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constant LSB_In : natural := 8;
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constant LSB_In : natural := 8;
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constant Nbit : natural := 12;
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constant Nbit : natural := 12;
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constant NbitW : natural := 24;
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constant NbitW : natural := 24;
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constant LSB_OUT : natural := 8;
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constant LSB_OUT : natural := 8;
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constant Nlayer : natural := 3;
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constant Nlayer : natural := 3;
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constant NbitOut : integer := 12 ;
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constant NbitOut : integer := 12 ;
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constant NumIn : integer := 1;
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constant NumIn : integer := 1;
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constant NumN : int_vector(Nlayer-1 downto 0) := assign_ints("2 3 1",Nlayer);
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constant NumN : int_vector(Nlayer-1 downto 0) := assign_ints("2 3 1",Nlayer);
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constant LSbit : int_vector(Nlayer-1 downto 0) := assign_ints("8 8 8",Nlayer);
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constant LSbit : int_vector(Nlayer-1 downto 0) := assign_ints("8 8 8",Nlayer);
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constant NbitO : int_vector(Nlayer-1 downto 0) := assign_ints("12 12 12",Nlayer);
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constant NbitO : int_vector(Nlayer-1 downto 0) := assign_ints("12 12 12",Nlayer);
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constant l_type : string := "SP PS SP"; -- Layer type of each layer
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constant l_type : string := "SP PS SP"; -- Layer type of each layer
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constant f_type : string := "siglu2 siglu2 siglu2"; -- Activation function type of each layer
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constant f_type : string := "sigmat sigmat sigmat"; -- Activation function type of each layer
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function real2stdlv (bitW : natural; din : real) return std_logic_vector;
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function real2stdlv (bitW : natural; din : real) return std_logic_vector;
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end support_pkg;
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end support_pkg;
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package body support_pkg is
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package body support_pkg is
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function real2stdlv (bitW : natural; din : real) return std_logic_vector is
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function real2stdlv (bitW : natural; din : real) return std_logic_vector is
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variable vres : signed(bitW-1 downto 0) := (others => '0');
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variable vres : signed(bitW-1 downto 0) := (others => '0');
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begin -- real2stdlv
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begin -- real2stdlv
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vres:= to_signed(integer(din*(2.0**(LSB_OUT))), bitW);
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vres:= to_signed(integer(din*(2.0**(LSB_OUT))), bitW);
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return std_logic_vector(vres);
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return std_logic_vector(vres);
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end real2stdlv;
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end real2stdlv;
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