| Line 146... |
Line 146... |
-- addresses. The CNTR values then differ from the memory address values,
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-- addresses. The CNTR values then differ from the memory address values,
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-- which can be useful to ensure that reading e.g. address 2**g_seq_dat_w
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-- which can be useful to ensure that reading e.g. address 2**g_seq_dat_w
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-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
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-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_pipeline_lib, common_ram_lib, mm_lib; -- init value for out_dat when diag_en = '0'
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, astron_pipeline_lib, astron_ram_lib, astron_mm_lib; -- init value for out_dat when diag_en = '0'
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE astron_ram_lib.common_ram_pkg.ALL;
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USE mm_lib.common_field_pkg.ALL;
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USE astron_mm_lib.common_field_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE work.diag_pkg.ALL;
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USE work.diag_pkg.ALL;
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ENTITY mms_diag_tx_seq IS
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ENTITY mms_diag_tx_seq IS
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GENERIC (
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GENERIC (
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| Line 288... |
Line 288... |
stat_reg_arr(I) <= ctrl_reg_arr(I); -- address 0, 1: control read back
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stat_reg_arr(I) <= ctrl_reg_arr(I); -- address 0, 1: control read back
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-- Status read only:
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-- Status read only:
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stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= tx_cnt_arr(I); -- address 2: read tx_cnt
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stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= tx_cnt_arr(I); -- address 2: read tx_cnt
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END PROCESS;
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END PROCESS;
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u_reg : ENTITY mm_lib.common_reg_r_w_dc
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u_reg : ENTITY astron_mm_lib.common_reg_r_w_dc
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GENERIC MAP (
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GENERIC MAP (
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g_cross_clock_domain => TRUE,
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g_cross_clock_domain => TRUE,
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g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
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g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
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g_reg => c_mm_reg
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g_reg => c_mm_reg
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)
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)
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| Line 312... |
Line 312... |
out_reg => ctrl_reg_arr(I)
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out_reg => ctrl_reg_arr(I)
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);
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);
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END GENERATE;
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END GENERATE;
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-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
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-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
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u_mem_mux : ENTITY mm_lib.common_mem_mux
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u_mem_mux : ENTITY astron_mm_lib.common_mem_mux
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GENERIC MAP (
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GENERIC MAP (
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g_broadcast => g_mm_broadcast,
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g_broadcast => g_mm_broadcast,
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g_nof_mosi => g_nof_streams,
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g_nof_mosi => g_nof_streams,
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g_mult_addr_w => c_mm_reg.adr_w
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g_mult_addr_w => c_mm_reg.adr_w
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)
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)
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| Line 365... |
Line 365... |
END IF;
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END IF;
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END LOOP;
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END LOOP;
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END PROCESS;
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END PROCESS;
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-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
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-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
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u_dp_pipeline_arr : ENTITY dp_pipeline_lib.dp_pipeline_arr
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u_dp_pipeline_arr : ENTITY astron_pipeline_lib.dp_pipeline_arr
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GENERIC MAP (
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GENERIC MAP (
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g_nof_streams => g_nof_streams
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g_nof_streams => g_nof_streams
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)
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)
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PORT MAP (
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PORT MAP (
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rst => dp_rst,
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rst => dp_rst,
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