| Line 18... |
Line 18... |
--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Purpose: Dual clock FIFO
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-- Purpose: Dual clock FIFO
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_fifo_lib;
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY common_fifo_dc IS
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ENTITY common_fifo_dc IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0; --c_tech_select_default;
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
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g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
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g_dat_w : NATURAL := 36;
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g_dat_w : NATURAL := 36;
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g_nof_words : NATURAL := 256 -- 36 * 256 = 1 M9K
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g_nof_words : NATURAL := 256 -- 36 * 256 = 1 M9K
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);
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);
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| Line 112... |
Line 112... |
IF rising_edge(rd_clk) THEN
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IF rising_edge(rd_clk) THEN
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rd_val <= nxt_rd_val;
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rd_val <= nxt_rd_val;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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u_fifo : ENTITY tech_fifo_lib.tech_fifo_dc
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u_fifo : ENTITY work.tech_fifo_dc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_dat_w => g_dat_w,
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g_dat_w => g_dat_w,
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g_nof_words => c_nof_words
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g_nof_words => c_nof_words
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)
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)
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