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Line 36... |
-- memory data word width.
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-- memory data word width.
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-- . The FIFO makes that the src_in.ready and snk_out.ready are not
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-- . The FIFO makes that the src_in.ready and snk_out.ready are not
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-- combinatorially connected, so this can ease the timing closure for the
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-- combinatorially connected, so this can ease the timing closure for the
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-- ready signal.
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-- ready signal.
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LIBRARY IEEE, common_pkg_lib, dp_components_lib, common_fifo_lib, dp_pkg_lib, technology_lib;
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LIBRARY IEEE, common_pkg_lib, dp_components_lib, dp_pkg_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY dp_fifo_core IS
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ENTITY dp_fifo_core IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_use_dual_clock : BOOLEAN := FALSE;
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g_use_dual_clock : BOOLEAN := FALSE;
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g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
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g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
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g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
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| Line 166... |
Line 166... |
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-- up stream use fifo almost full to control snk_out.ready
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-- up stream use fifo almost full to control snk_out.ready
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nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
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nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
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gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
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gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
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u_common_fifo_sc : ENTITY common_fifo_lib.common_fifo_sc
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u_common_fifo_sc : ENTITY work.common_fifo_sc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_note_is_ful => g_note_is_ful,
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g_note_is_ful => g_note_is_ful,
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g_use_lut => g_use_lut_sc,
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g_use_lut => g_use_lut_sc,
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g_dat_w => c_fifo_dat_w,
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g_dat_w => c_fifo_dat_w,
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| Line 191... |
Line 191... |
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fifo_wr_usedw <= fifo_rd_usedw;
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fifo_wr_usedw <= fifo_rd_usedw;
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END GENERATE;
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END GENERATE;
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gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
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gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
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u_common_fifo_dc : ENTITY common_fifo_lib.common_fifo_dc
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u_common_fifo_dc : ENTITY work.common_fifo_dc
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_dat_w => c_fifo_dat_w,
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g_dat_w => c_fifo_dat_w,
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g_nof_words => g_fifo_size
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g_nof_words => g_fifo_size
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)
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)
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