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-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
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-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
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-- Description: See dp_fifo_core.vhd.
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-- Description: See dp_fifo_core.vhd.
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, technology_lib;
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY dp_fifo_dc IS
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ENTITY dp_fifo_dc IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_bsn_w : NATURAL := 1;
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g_bsn_w : NATURAL := 1;
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g_empty_w : NATURAL := 1;
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g_empty_w : NATURAL := 1;
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g_channel_w : NATURAL := 1;
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g_channel_w : NATURAL := 1;
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g_error_w : NATURAL := 1;
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g_error_w : NATURAL := 1;
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