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-- Engineer : RyuShinHyung
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-- Engineer : RyuShinHyung
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--
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--
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-- Create Date : 02/23/2005
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-- Create Date : 02/23/2005
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-- Design Name :
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-- Design Name :
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-- Module Name : DEC8B10B - RTL
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-- Module Name : DEC8B10B - RTL
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-- Project Name : DSP Application
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-- Project Name : Fiber Optic Application
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--
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--
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-- Revision
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-- Revision
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Comments : General DEC8B10B
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-- 1.00 - publishing on the opencores.org
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-- 1.01 - eliminate needing the VECTLIB.vhd in the original revision.(20110424)
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.vect_pack.ALL;
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entity DEC8B10B is
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entity DEC8B10B is
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port
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port
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(
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(
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CLK_IN : IN STD_LOGIC;
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CLK_IN : IN STD_LOGIC;
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ENCODE_IN : in STD_LOGIC_VECTOR(9 downto 0);
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ENCODE_IN : in STD_LOGIC_VECTOR(9 downto 0);
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CTRL_OUT : out STD_LOGIC;
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CTRL_OUT : out STD_LOGIC;
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DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
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DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
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);
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);
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--attribute FAST : string;
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--attribute SLOW : string;
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--attribute FAST of DEC8B10B : entity is "TRUE";
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--attribute SLOW of DEC8B10B : entity is "FALSE";
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end DEC8B10B;
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end DEC8B10B;
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architecture RTL of DEC8B10B is
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architecture RTL of DEC8B10B is
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constant DEC8b10bERR : std_logic_vector := "100000000";
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constant DEC8b10bERR : std_logic_vector := "100000000";
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