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/*
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* This is the simulation file for Atmel XMEGA CPU IP.
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*
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* Copyright (C) 2017 Iulian Gheorghiu
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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`timescale 1ns / 1ps
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//`include "ddr3_v.v"
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/* For Attiny 26 */
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//`define BUS_ADDR_PGM_LEN_SIM 11 /* < in address lines 2KWords */
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//`define BUS_ADDR_DATA_LEN_SIM 8 /* < in address lines 256Bytes data address space */
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//`define DATA_MEM_SIZE_LEN_SIM 7 /* < in address lines 128Bytes */
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//`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd128 /* < in bytes ( 128 bytes to let space for IO usage )*/
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/* For ATXmega */
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`define BUS_ADDR_PGM_LEN_SIM 16 /* < in address lines 64KWords */
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`define BUS_ADDR_DATA_LEN_SIM 16 /* < in address lines 64KBytes data address space */
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`define DATA_MEM_SIZE_LEN_SIM 12 /* < in address lines 4KByte */
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`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd8192 /* < in bytes ( 8192 bytes is the standard atxmega reserved address for IO usage )*/
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`define USE_HDMI_OUTPUT
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`define DDR3_ADDR_BUS_LEN 15
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module sim_uc(
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//`DDR3_TOP
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);
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//`DDR3_IO
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reg rst = 0;
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/*ddr3 ddr3_inst(
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`DDR3_CONNECT
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);*/
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reg int1 = 0;
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reg int2 = 0;
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reg int3 = 0;
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wire _int1 = int1;
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wire _int2 = int2;
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wire _int3 = int3;
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wire [4:0]int = 0;
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wire sys_rst;
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wire [7:0]port_out;
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wire [7:0]port_in = port_out;
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wire UART_TXD;
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wire UART_RXD = UART_TXD;
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wire hdmi_tx_cec;
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wire hdmi_tx_clk_n;
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wire hdmi_tx_clk_p;
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wire hdmi_tx_hpd;
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wire hdmi_tx_rscl;
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wire hdmi_tx_rsda;
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wire [2:0]hdmi_tx_n;
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wire [2:0]hdmi_tx_p;
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reg core_clk = 0;
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reg ram_clk = 0;
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always #(1) ram_clk <= ~ram_clk; // clocking device
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always @ (posedge ram_clk)
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begin
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core_clk <= ~core_clk;
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end
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wire lcd_clk = core_clk;
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//wire pgm_re;
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wire [`BUS_ADDR_PGM_LEN_SIM-1:0] pgm_addr;
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wire [15:0] pgm_data;
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wire data_re;
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wire data_we;
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wire [`BUS_ADDR_DATA_LEN_SIM-1:0] data_addr;
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wire [7:0]data_in;
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wire [7:0]data_out;
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wire io_re;
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wire io_we;
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wire [5:0] io_addr;
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wire [7:0] io_in;
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wire [7:0] io_out;
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//assign data_addr = data_re | data_we ? 'bz : 0;
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wire ram_data_sel = data_addr >= `DATA_ADDR_RESERVED_AT_BOTTOM_SIM;
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wire [`BUS_ADDR_DATA_LEN_SIM-1:0]ram_offset = `DATA_ADDR_RESERVED_AT_BOTTOM_SIM;
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wire [`DATA_MEM_SIZE_LEN_SIM-1:0]ram_addr_bus = data_addr - ram_offset;
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wire rtc_int;
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wire int_pio_a;
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wire int_pio_b;
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wire int_pio_c;
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wire int_pio_d;
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wire int_pio_e;
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wire int_pio_f;
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wire int_uart_a_rx_rcv;
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wire int_uart_a_tx_compl;
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wire int_uart_a_tx_buff_empty;
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wire int_spi_a;
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wire [10:0]int_rst;
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initial begin
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rst = 0;
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#1;
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rst = 1;
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#1;
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rst = 0;
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//port_out = 8'haa;
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#110000;
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int1 = 1;
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//int2 = 1;
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//int3 = 1;
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#20;
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int1 = 0;
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int2 = 0;
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int3 = 0;
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#1200000;
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$finish;
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end
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rtc_s # (
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.ADDRESS('h40),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM),
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.CNT_SIZE(32)
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) rtc (
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.int(rtc_int),
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.int_rst(int_rst[0])
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);
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pio_s # (
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.DINAMIC_IN_OUT_CONFIG("TRUE"),
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.IN_OUT_MASK_CONFIG(8'h00),
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.USE_INTERRUPTS("TRUE"),
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.DINAMIC_INTERRUPT_CONFIG("TRUE"),
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.INTERRUPT_MASK_CONFIG(8'h07),
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.INTERRUPT_UP_DN_EDGE_DETECT(8'h07),
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.INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),
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.BUS_KEPPER_EN_MASK(8'b00000000),
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.BUS_PULL_UP_EN_MASK(8'b00000000),
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.BUS_PULL_DN_EN_MASK(8'b00000000),
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.ADDRESS('h60),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
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) pio_port_A (
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.io({int, _int3, _int2, _int1}),
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.int(int_pio_a),
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.int_rst(int_rst[1])
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);
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pio_s # (
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.DINAMIC_IN_OUT_CONFIG("FALSE"),
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.IN_OUT_MASK_CONFIG(8'h00),
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.USE_INTERRUPTS("FALSE"),
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.DINAMIC_INTERRUPT_CONFIG("FALSE"),
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.INTERRUPT_MASK_CONFIG(8'h00),
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.INTERRUPT_UP_DN_EDGE_DETECT(8'h00),
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.INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),
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.BUS_KEPPER_EN_MASK(8'b00000000),
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.BUS_PULL_UP_EN_MASK(8'b00000000),
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.BUS_PULL_DN_EN_MASK(8'b00000000),
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.ADDRESS('h80),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
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) pio_port_B (
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.io(port_in),
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.int(int_pio_b),
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.int_rst(int_rst[2])
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);
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pio_s # (
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.DINAMIC_IN_OUT_CONFIG("FALSE"),
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.IN_OUT_MASK_CONFIG(8'hFF),
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.USE_INTERRUPTS("FALSE"),
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.DINAMIC_INTERRUPT_CONFIG("FALSE"),
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.INTERRUPT_MASK_CONFIG(8'h00),
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.INTERRUPT_UP_DN_EDGE_DETECT(8'h00),
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.INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),
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.BUS_KEPPER_EN_MASK(8'b00000000),
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.BUS_PULL_UP_EN_MASK(8'b00000000),
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.BUS_PULL_DN_EN_MASK(8'b00000000),
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.ADDRESS('hA0),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
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) pio_port_C (
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.io(port_out),
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.int(int_pio_c),
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.int_rst(int_rst[3])
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);
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//`ifdef _0_
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uart_s # (
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.BAUDRATE_COUNTER_LENGTH(12),
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.DINAMIC_BAUDRATE("TRUE"),
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.BAUDRATE_DIVIDER((1000 / 24) / 16 / 19200),
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.ADDRESS('hC0),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
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) uart_A (
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.int_rx_rcv(int_uart_a_rx_rcv),
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.int_tx_compl(int_uart_a_tx_compl),
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.int_tx_buff_empty(int_uart_a_tx_buff_empty),
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.tx(UART_TXD),
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.rx(UART_RXD)
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);
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wire oled_sclk;
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wire oled_sdin;
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spi_s #(
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.DINAMIC_BAUDRATE("TRUE"),
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.BAUDRATE_DIVIDER(8),
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.ADDRESS('h600),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
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)spi_A(
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.int(int_spi_a),
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.sck(oled_sclk),/* SPI 'sck' signal (output) */
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.mosi(oled_sdin),/* SPI 'mosi' signal (output) */
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.miso(1'b1),/* SPI 'miso' signal (input) */
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.ss()/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */
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);
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wire ja_scl;
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wire ja_sda;
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twi_s #(
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.DINAMIC_BAUDRATE("TRUE"),
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.BAUDRATE_DIVIDER(255),
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.ADDRESS('h800),
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.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
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)twi_inst(
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.rst(sys_rst),
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.clk(core_clk),
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.addr(data_addr),
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.wr(data_we),
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.rd(data_re),
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.bus_in(data_out),
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.bus_out(data_in),
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.int_tx_cmpl(),
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.int_rx_cmpl(),
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.int_tx_rst(),
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.int_rx_rst(),
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.scl(ja_scl),
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.sda(ja_sda)
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);
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wire lcd_h_int;
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wire lcd_v_int;
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wire lcd_de;
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wire [7:0]ja_int;
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wire [7:0]jb_int;
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wire [7:0]jc_int;
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wire lcd_clk_10;
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`ifndef USE_HDMI_OUTPUT
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assign ja = {ja_int[7:1], lcd_clk_10};
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assign jb = {jb_int[7:1], lcd_h_int};
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assign jc = {jc_int[7:1], lcd_v_int};
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`endif
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lcd # (
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.MASTER("TRUE"),
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.DEBUG(""),//"PATERN_RASTER"
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.DISPLAY_CFG("1280_720_60_DISPLAY_74_25_Mhz"),
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.ADDRESS('hE0),
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.BUS_VRAM_ADDR_LEN(24),
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.BUS_VRAM_DATA_LEN(8),
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.BUS_ADDR_DATA_LEN(16),
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.DINAMIC_CONFIG("FALSE"),
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.VRAM_BASE_ADDRESS_CONF(0),
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/* This timings are for AT070TN92 LCD display module but is not tacken in account because we will load a default setup with DISPLAY_CFG parameter.*/
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.H_RES_CONF(720),
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.H_BACK_PORCH_CONF(138),
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.H_FRONT_PORCH_CONF(16),
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.H_PULSE_WIDTH_CONF(62),
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.V_RES_CONF(480),
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.V_BACK_PORCH_CONF(45),
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.V_FRONT_PORCH_CONF(9),
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.V_PULSE_WIDTH_CONF(6),
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.PIXEL_SIZE_CONF(16),
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.HSYNK_INVERTED_CONF(1'b0),
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.VSYNK_INVERTED_CONF(1'b0),
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.DATA_ENABLE_INVERTED_CONF(1'b0),
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.DEDICATED_VRAM_SIZE(800 * 480)
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)lcd_inst(
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.rst(sys_rst),
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.ctrl_clk(core_clk),
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.ctrl_addr(data_addr),
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.ctrl_wr(data_we),
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.ctrl_rd(data_re),
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.ctrl_data_in(data_out),
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.ctrl_data_out(data_in),
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.vmem_addr(ram_addr_bus),
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.vmem_in(data_out),
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.vmem_out(data_in),
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.vmem_rd(1'b0),
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.vmem_wr(data_we & ram_data_sel),
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`ifdef USE_HDMI_OUTPUT
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.lcd_clk(lcd_clk_10),
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`else
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.lcd_clk(lcd_clk),
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`endif
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.lcd_h_synk(lcd_h_int),
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.lcd_v_synk(lcd_v_int),
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.lcd_r(ja_int),
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.lcd_g(jb_int),
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.lcd_b(jc_int),
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.lcd_de(lcd_de)
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);
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`ifdef USE_HDMI_OUTPUT
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hdmi_out # (
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.PLATFORM("XILINX_ARTIX_7")
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)hdmi_out_inst(
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.rst(sys_rst),
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.clk(lcd_clk),
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.hdmi_tx_cec(hdmi_tx_cec),
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.hdmi_tx_clk_n(hdmi_tx_clk_n),
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.hdmi_tx_clk_p(hdmi_tx_clk_p),
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.hdmi_tx_hpd(hdmi_tx_hpd),
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.hdmi_tx_rscl(hdmi_tx_rscl),
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.hdmi_tx_rsda(hdmi_tx_rsda),
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.hdmi_tx_n(hdmi_tx_n),
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.hdmi_tx_p(hdmi_tx_p),
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.lcd_clk_out(lcd_clk_10),
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.lcd_h_synk(lcd_h_int),
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.lcd_v_synk(lcd_v_int),
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.lcd_r('hAA),
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.lcd_g('hDB),
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.lcd_b('h24),
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.lcd_de(lcd_de)
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);
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`endif
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//`endif //!_0_
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rom #(
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.ADDR_ROM_BUS_WIDTH(`BUS_ADDR_PGM_LEN_SIM),
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.ROM_PATH("core1ROM.mem"),
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.SYNCHRONOUS("FALSE")
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)rom(
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.clk(core_clk),
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.a(pgm_addr),
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.d(pgm_data)
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);
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ram #(
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.ADDR_BUS_WIDTH(`DATA_MEM_SIZE_LEN_SIM),
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.RAM_PATH(""),
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.SYNCHRONOUS("TRUE")
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)ram(
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.clk(core_clk),
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.re(data_re & ram_data_sel),
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.we(data_we & ram_data_sel),
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.a(ram_addr_bus),
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.d_in(data_out),
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.d_out(data_in)
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);
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mega_core #(
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.CORE_CONFIG("XMEGA"),// Supported: "REDUCED", "MINIMAL", "CLASSIC_8K", "CLASSIC_128K", "ENHANCED_8K", "ENHANCED_128K", "ENHANCED_4M", "XMEGA"
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.BUS_ADDR_PGM_WIDTH(`BUS_ADDR_PGM_LEN_SIM),
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.BUS_ADDR_DATA_WIDTH(`BUS_ADDR_DATA_LEN_SIM),
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.USE_BRAM_ROM("FALSE"),
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.WATCHDOG_CNT_WIDTH(21),/* If is 0 the watchdog is disabled */
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.VECTOR_INT_TABLE_SIZE(10),
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.STORE_INTERUPTS("FALSE"),
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.MAP_REGS_IN_TO_SRAM_SECTION("FALSE")
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)core(
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.rst(rst),
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.sys_rst(sys_rst),/* Output reset provided by core thru watchdog to the rest of the system */
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.clk(core_clk),
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.clk_wdt(core_clk),
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.pgm_addr(pgm_addr),
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.pgm_data(pgm_data),
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.data_re(data_re),
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.data_we(data_we),
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.data_addr(data_addr),
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.data_in(data_in),
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.data_out(data_out),
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.io_re(io_re),
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.io_we(io_we),
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.io_addr(io_addr),
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.io_in(io_in),
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.io_out(io_out),
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.int_sig({int_uart_a_tx_buff_empty, int_uart_a_tx_compl, int_uart_a_rx_rcv, int_spi_a, int_pio_f, int_pio_e, int_pio_d, int_pio_c, int_pio_b, int_pio_a, rtc_int}),
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.int_rst(int_rst),
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.wdt_rst_out()
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);
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endmodule
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No newline at end of file
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No newline at end of file
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