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[/] [avs_aes/] [trunk/] [rtl/] [VHDL/] [mixcol.vhd] - Diff between revs 10 and 11

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-- This file is part of the project  avs_aes
 
-- see: http://opencores.org/project,avs_aes
 
--
 
-- description:
 
-- This is only the entity to the architectures fwd and INV of mixcolumn as
 
-- they have the same interface
 
--
 
-------------------------------------------------------------------------------
 
--
 
-- Author(s):
 
--         Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
 
--
 
--------------------------------------------------------------------------------
 
-- Copyright (c) 2009, Authors and opencores.org
 
-- All rights reserved.
 
--
 
-- Redistribution and use in source and binary forms, with or without modification,
 
-- are permitted provided that the following conditions are met:
 
--    * Redistributions of source code must retain the above copyright notice,
 
--    this list of conditions and the following disclaimer.
 
--    * Redistributions in binary form must reproduce the above copyright notice,
 
--    this list of conditions and the following disclaimer in the documentation
 
--    and/or other materials provided with the distribution.
 
--    * Neither the name of the organization nor the names of its contributors
 
--    may be used to endorse or promote products derived from this software without
 
--    specific prior written permission.
 
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
 
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 
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-- THE POSSIBILITY OF SUCH DAMAGE
 
-------------------------------------------------------------------------------
 
-- version management:
 
-- $Author$
 
-- $Date$
 
-- $Revision$                   
 
-------------------------------------------------------------------------------
 
 
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
 
 
 
 
library avs_aes_lib;
 
use avs_aes_lib.avs_aes_pkg.all;
 
 
 
entity Mixcol is
 
        port (
 
                col_in  : in  DWORD;                    -- one column of the state
 
                col_out : out DWORD                     -- output column
 
                );
 
end entity Mixcol;
 
 
 
 
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