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--------------------------------------------------------------------------------
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-- This file is part of the project avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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-- description:
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-- instantiation of an Altera M4K blockram as dual port ROM
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-- they have the nice feature of allowing an initialization file. with the
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-- generic rominitfile it is possible to select the encryption or decryption
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-- version sbox.hex and sbox_inv.hex
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-- Only 8-Bit dual port was supported on CyloneII... this is why we need a lot
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-- of blockrams in aes_core.vhd AND keyexpansionV2.vhd
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--
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-------------------------------------------------------------------------------
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-- Todo:
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--
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-- Author(s):
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-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Authors and opencores.org
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- * Neither the name of the organization nor the names of its contributors
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-- may be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-- version management:
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-- $Author$
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-- $Date$
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-- $Revision$
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library altera_mf;
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use altera_mf.all;
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library avs_aes_lib;
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use avs_aes_lib.avs_aes_pkg.all;
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architecture M4k of sbox is
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---------------------------------------------------------------------------
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-- Altera Stuff
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-- ( I don't want this in avs_aes_pkg because it is vendor specific)
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---------------------------------------------------------------------------
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component altsyncram
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generic (
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ADDRESS_REG_B : STRING;
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CLOCK_ENABLE_INPUT_A : STRING;
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CLOCK_ENABLE_INPUT_B : STRING;
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CLOCK_ENABLE_OUTPUT_A : STRING;
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CLOCK_ENABLE_OUTPUT_B : STRING;
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INDATA_REG_B : STRING;
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INIT_FILE : STRING;
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INTENDED_DEVICE_FAMILY : STRING;
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LPM_TYPE : STRING;
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NUMWORDS_A : NATURAL;
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NUMWORDS_B : NATURAL;
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OPERATION_MODE : STRING;
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OUTDATA_ACLR_A : STRING;
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OUTDATA_ACLR_B : STRING;
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OUTDATA_REG_A : STRING;
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OUTDATA_REG_B : STRING;
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POWER_UP_UNINITIALIZED : STRING;
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WIDTHAD_A : NATURAL;
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WIDTHAD_B : NATURAL;
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WIDTH_A : NATURAL;
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WIDTH_B : NATURAL;
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WIDTH_BYTEENA_A : NATURAL;
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WIDTH_BYTEENA_B : NATURAL;
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WRCONTROL_WRADDRESS_REG_B : STRING
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);
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port (
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wren_a : in STD_LOGIC;
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wren_b : in STD_LOGIC;
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clock0 : in STD_LOGIC;
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address_a : in STD_LOGIC_VECTOR (7 downto 0);
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address_b : in STD_LOGIC_VECTOR (7 downto 0);
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q_a : out STD_LOGIC_VECTOR (7 downto 0);
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q_b : out STD_LOGIC_VECTOR (7 downto 0);
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data_a : in STD_LOGIC_VECTOR (7 downto 0);
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data_b : in STD_LOGIC_VECTOR (7 downto 0)
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);
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end component;
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begin
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assign_inverse : if INVERSE generate
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m4kblock_inv : altsyncram
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generic map (
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address_reg_b => "CLOCK0",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_b => "BYPASS",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_b => "BYPASS",
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indata_reg_b => "CLOCK0",
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init_file => "sbox_inv.hex",
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intended_device_family => "Cyclone II",
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lpm_type => "altsyncram",
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numwords_a => 256,
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numwords_b => 256,
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operation_mode => "BIDIR_DUAL_PORT",
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outdata_aclr_a => "NONE",
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outdata_aclr_b => "NONE",
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outdata_reg_a => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
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outdata_reg_b => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
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power_up_uninitialized => "FALSE",
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widthad_a => 8,
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widthad_b => 8,
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width_a => 8,
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width_b => 8,
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width_byteena_a => 1,
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width_byteena_b => 1,
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wrcontrol_wraddress_reg_b => "CLOCK0"
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)
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port map (
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wren_a => '0', -- we don't write to ROM
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wren_b => '0', -- we don't write to ROM
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clock0 => clk,
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data_a => (others => '0'), -- dumb compiler wants it anyway
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data_b => (others => '0'), -- dumb compiler wants it anyway
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address_a => address_a,
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address_b => address_b,
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q_a => q_a,
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q_b => q_b
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);
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end generate assign_inverse;
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assign_encrypt : if not INVERSE generate
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m4kblock_fwd : altsyncram
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generic map (
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address_reg_b => "CLOCK0",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_b => "BYPASS",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_b => "BYPASS",
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indata_reg_b => "CLOCK0",
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init_file => "sbox.hex",
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intended_device_family => "Cyclone II",
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lpm_type => "altsyncram",
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numwords_a => 256,
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numwords_b => 256,
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operation_mode => "BIDIR_DUAL_PORT",
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outdata_aclr_a => "NONE",
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outdata_aclr_b => "NONE",
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outdata_reg_a => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
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outdata_reg_b => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
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power_up_uninitialized => "FALSE",
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widthad_a => 8,
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widthad_b => 8,
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width_a => 8,
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width_b => 8,
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width_byteena_a => 1,
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width_byteena_b => 1,
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wrcontrol_wraddress_reg_b => "CLOCK0"
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)
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port map (
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wren_a => '0', -- we don't write to ROM
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wren_b => '0', -- we don't write to ROM
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clock0 => clk,
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data_a => (others => '0'), -- dumb compiler wants it anyway
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data_b => (others => '0'), -- dumb compiler wants it anyway
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address_a => address_a,
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address_b => address_b,
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q_a => q_a,
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q_b => q_b
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);
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end generate assign_encrypt;
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end M4k;
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No newline at end of file
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No newline at end of file
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