| Line 123... |
Line 123... |
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OUTFILE PREFIX.v
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OUTFILE PREFIX.v
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INCLUDE def_axi_master.txt
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INCLUDE def_axi_master.txt
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ITER IDX ID_NUM
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ITER IX ID_NUM
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module PREFIX(PORTS);
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module PREFIX(PORTS);
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`include "prgen_rand.v"
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`include "prgen_rand.v"
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input clk;
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input clk;
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| Line 141... |
Line 140... |
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//random parameters
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//random parameters
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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wire GROUP_STUB_AXI_IX;
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wire GROUP_STUB_AXI_IDX;
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wire idle_IX;
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wire idle_IDX;
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wire scrbrd_empty_IX;
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wire scrbrd_empty_IDX;
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always @(*)
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always @(*)
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begin
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begin
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#FFD;
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#FFD;
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PREFIX_singleIX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
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PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
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end
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end
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assign idle = CONCAT(idle_IX &);
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assign idle = CONCAT(idle_IDX &);
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assign scrbrd_empty = CONCAT(scrbrd_empty_IX &);
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assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
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CREATE axi_master_single.v
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CREATE axi_master_single.v
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LOOP IX ID_NUM
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LOOP IDX ID_NUM
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PREFIX_single #(IX, IDIX_VAL, CMD_DEPTH)
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PREFIX_single #(IDX, ID_BITS'GROUP_AXI_ID[IDX], CMD_DEPTH)
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PREFIX_singleIX(
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PREFIX_singleIDX(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_STUB_AXI(GROUP_STUB_AXI_IX),
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.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
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.idle(idle_IX),
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.idle(idle_IDX),
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.scrbrd_empty(scrbrd_empty_IX)
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.scrbrd_empty(scrbrd_empty_IDX)
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);
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);
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ENDLOOP IX
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ENDLOOP IDX
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IFDEF TRUE(ID_NUM==1)
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IFDEF TRUE(ID_NUM==1)
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assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
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assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
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assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
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assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
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ELSE TRUE(ID_NUM==1)
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ELSE TRUE(ID_NUM==1)
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CREATE ic.v \\
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CREATE ic.v \\
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DEFCMD(SWAP.GLOBAL PARENT PREFIX) \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
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DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
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DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
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DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
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DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
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DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS)
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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LOOP IX ID_NUM
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DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
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LOOP IDX ID_NUM
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STOMP NEWLINE
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STOMP NEWLINE
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DEFCMD(LOOP.GLOBAL MIX_IDX 1) \\
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DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
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DEFCMD(SWAP.GLOBAL ID_MIX_ID0 ID_BITSIDIX_VAL)
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DEFCMD(GROUP_AXI_ID[IDX]) \\
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ENDLOOP IX
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DEFCMD(})
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ENDLOOP IDX
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PREFIX_ic PREFIX_ic(
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PREFIX_ic PREFIX_ic(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.MIX_GROUP_STUB_AXI(GROUP_STUB_AXI_IX),
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.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
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.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
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.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
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STOMP ,
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STOMP ,
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);
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);
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| Line 220... |
Line 222... |
task enable;
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task enable;
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input [31:0] master_num;
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input [31:0] master_num;
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begin
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begin
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check_master_num("enable", master_num);
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check_master_num("enable", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.enable = 1;
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IDX : PREFIX_singleIDX.enable = 1;
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endcase
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endcase
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end
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end
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endtask
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endtask
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task enable_all;
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task enable_all;
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begin
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begin
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PREFIX_singleIX.enable = 1;
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PREFIX_singleIDX.enable = 1;
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end
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end
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endtask
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endtask
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task write_single;
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task write_single;
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input [31:0] master_num;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
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begin
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begin
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check_master_num("write_single", master_num);
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check_master_num("write_single", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.write_single(addr, wdata);
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IDX : PREFIX_singleIDX.write_single(addr, wdata);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task read_single;
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task read_single;
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| Line 250... |
Line 252... |
input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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output [DATA_BITS-1:0] rdata;
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output [DATA_BITS-1:0] rdata;
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begin
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begin
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check_master_num("read_single", master_num);
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check_master_num("read_single", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.read_single(addr, rdata);
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IDX : PREFIX_singleIDX.read_single(addr, rdata);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task check_single;
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task check_single;
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| Line 262... |
Line 264... |
input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] expected;
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input [DATA_BITS-1:0] expected;
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begin
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begin
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check_master_num("check_single", master_num);
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check_master_num("check_single", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.check_single(addr, expected);
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IDX : PREFIX_singleIDX.check_single(addr, expected);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task write_and_check_single;
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task write_and_check_single;
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| Line 274... |
Line 276... |
input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] data;
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input [DATA_BITS-1:0] data;
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begin
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begin
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check_master_num("write_and_check_single", master_num);
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check_master_num("write_and_check_single", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.write_and_check_single(addr, data);
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IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task insert_wr_cmd;
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task insert_wr_cmd;
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| Line 287... |
Line 289... |
input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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begin
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begin
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check_master_num("insert_wr_cmd", master_num);
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check_master_num("insert_wr_cmd", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.insert_wr_cmd(addr, len, size);
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IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task insert_rd_cmd;
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task insert_rd_cmd;
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| Line 300... |
Line 302... |
input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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begin
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begin
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check_master_num("insert_rd_cmd", master_num);
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check_master_num("insert_rd_cmd", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.insert_rd_cmd(addr, len, size);
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IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task insert_wr_data;
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task insert_wr_data;
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input [31:0] master_num;
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input [31:0] master_num;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
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begin
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begin
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check_master_num("insert_wr_data", master_num);
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check_master_num("insert_wr_data", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.insert_wr_data(wdata);
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IDX : PREFIX_singleIDX.insert_wr_data(wdata);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task insert_wr_incr_data;
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task insert_wr_incr_data;
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| Line 324... |
Line 326... |
input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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begin
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begin
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check_master_num("insert_wr_incr_data", master_num);
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check_master_num("insert_wr_incr_data", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.insert_wr_incr_data(addr, len, size);
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IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task insert_rand_chk;
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task insert_rand_chk;
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input [31:0] master_num;
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input [31:0] master_num;
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input [31:0] burst_num;
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input [31:0] burst_num;
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begin
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begin
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check_master_num("insert_rand_chk", master_num);
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check_master_num("insert_rand_chk", master_num);
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case (master_num)
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case (master_num)
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IX : PREFIX_singleIX.insert_rand_chk(burst_num);
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IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task insert_rand;
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task insert_rand;
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input [31:0] burst_num;
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input [31:0] burst_num;
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ITER IDX ID_NUM
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reg [31:0] burst_numIDX;
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reg [31:0] burst_numIDX;
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integer remain;
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integer remain;
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begin
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begin
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remain = burst_num;
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remain = burst_num;
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LOOP IDX ID_NUM
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LOOP IDX ID_NUM
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