| Line 391... |
Line 391... |
begin
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begin
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bytes = 1'b1 << size;
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bytes = 1'b1 << size;
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wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
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wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
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data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
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data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
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add_data = {DATA_BITS/8{data_cnt}};
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add_data = {DATA_BITS/8{data_cnt}};
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next_data = base_data + add_data;
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next_data = (use_addr_base ? addr : base_data) + add_data;
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insert_wr_data(next_data);
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insert_wr_data(next_data);
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valid_cnt = valid_cnt+1;
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valid_cnt = valid_cnt+1;
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end
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end
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//insert command
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//insert command
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insert_wr_cmd(addr, len, size);
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insert_wr_cmd(addr, len, size);
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| Line 440... |
Line 440... |
begin
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begin
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bytes = 1'b1 << size;
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bytes = 1'b1 << size;
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wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
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wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
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data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
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data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
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add_data = {DATA_BITS/8{data_cnt}};
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add_data = {DATA_BITS/8{data_cnt}};
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next_data = base_data + add_data;
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next_data = (use_addr_base ? addr : base_data) + add_data;
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next_addr = addr + (bytes * valid_cnt);
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next_addr = addr + (bytes * valid_cnt);
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strb = (1 << (bytes*8)) - 1;
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strb = (1 << (bytes*8)) - 1;
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mask = strb << (next_addr[DATA_LOG-1:0]*8);
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mask = strb << (next_addr[DATA_LOG-1:0]*8);
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insert_scrbrd(next_addr, next_data, mask);
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insert_scrbrd(next_addr, next_data, mask);
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valid_cnt = valid_cnt+1;
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valid_cnt = valid_cnt+1;
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| Line 613... |
Line 613... |
begin
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begin
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read_single_ack(addr, rdata, resp);
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read_single_ack(addr, rdata, resp);
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end
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end
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endtask
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endtask
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|
|
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task check_single;
|
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input [ADDR_BITS-1:0] addr;
|
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input [DATA_BITS-1:0] expected;
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|
|
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reg [1:0] resp;
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reg [DATA_BITS-1:0] rdata;
|
|
begin
|
|
read_single_ack(addr, rdata, resp);
|
|
if (rdata !== expected)
|
|
$display("MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
|
|
end
|
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endtask
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|
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task write_and_check_single;
|
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input [ADDR_BITS-1:0] addr;
|
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input [DATA_BITS-1:0] data;
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|
|
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begin
|
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write_single(addr, data);
|
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check_single(addr, data);
|
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end
|
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endtask
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|
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task write_single;
|
task write_single;
|
input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
|
|
|
reg [1:0] resp;
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reg [1:0] resp;
|
