URL https://opencores.org/ocsvn/biriscv/biriscv/trunk

Subversion Repositories biriscv

[/] [biriscv/] [trunk/] [README.md] - Diff between revs 2 and 4

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`A sequence showing execution of 2 instructions per cycle;`	`A sequence showing execution of 2 instructions per cycle;`
`![Dual-Issue](docs/dual_issue.png)`	`![Dual-Issue](docs/dual_issue.png)`

`## Documentation`	`## Documentation`
`* [Configuration](http://github.com/ultraembedded/biriscv/docs/configuration.md)`	`* [Configuration](https://github.com/ultraembedded/biriscv/blob/master/docs/configuration.md)`
`* [Booting Linux](http://github.com/ultraembedded/biriscv/docs/linux.md)`	`* [Booting Linux](https://github.com/ultraembedded/biriscv/blob/master/docs/linux.md)`
`* [Integration](http://github.com/ultraembedded/biriscv/docs/integration.md)`	`* [Integration](https://github.com/ultraembedded/biriscv/blob/master/docs/integration.md)`
`* [Custom Features](http://github.com/ultraembedded/biriscv/docs/custom.md)`	`* [Custom Features](https://github.com/ultraembedded/biriscv/blob/master/docs/custom.md)`

`## Similar Cores`	`## Similar Cores`
`* [SiFive E76](https://www.sifive.com/cores/e76)`	`* [SiFive E76](https://www.sifive.com/cores/e76)`
`* RV32IMAFC`	`* RV32IMAFC`
`* Dual issue in-order 8 stage pipeline`	`* Dual issue in-order 8 stage pipeline`