//========================================================================
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//========================================================================
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//
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//
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// tb_ca_prng.v
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// tb_ca_prng.v
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// ------------
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// ------------
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// Testbench for the rule cellular automata based PRNG ca_prng.
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// Testbench for the rule cellular automata based PRNG ca_prng.
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// This version is for ca_prng with 32 bit pattern output.
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// This version is for ca_prng with 32 bit pattern output.
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//
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//
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//
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//
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// Author: Joachim Strombergson
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// Author: Joachim Strombergson
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// Copyright (c) 2008, InformAsic AB
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// Copyright (c) 2008, InformAsic AB
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// modification, are permitted provided that the following conditions
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// are met:
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// are met:
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//
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//
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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//
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//
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// * Redistributions in binary form must reproduce the above
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials
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// disclaimer in the documentation and/or other materials
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// provided with the distribution.
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// provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY InformAsic AB ''AS IS'' AND ANY EXPRESS
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// THIS SOFTWARE IS PROVIDED BY InformAsic AB ''AS IS'' AND ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL InformAsic AB BE LIABLE FOR ANY
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// ARE DISCLAIMED. IN NO EVENT SHALL InformAsic AB BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//========================================================================
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//========================================================================
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|
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Simulator directives
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// Simulator directives
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//
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//
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// Timescale etc.
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// Timescale etc.
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// tb_rule30
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// tb_ca_prng
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//
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//
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// The self contained testbench module.
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// The self contained testbench module.
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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module tb_ca_prng();
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module tb_ca_prng();
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|
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Parameter declarations
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// Parameter declarations
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// CLK_HALF_PERIOD
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// CLK_HALF_PERIOD
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// Half period (assuming 50/50 duty cycle) in ns.
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// Half period (assuming 50/50 duty cycle) in ns.
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parameter CLK_HALF_PERIOD = 5;
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parameter CLK_HALF_PERIOD = 5;
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// RULE_2
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// RULE_2
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// This rule generates a single angled line.
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// This rule generates a single angled line.
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// See the following link for more info:
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// See the following link for more info:
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// http://mathworld.wolfram.com/ElementaryCellularAutomaton.html
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// http://mathworld.wolfram.com/ElementaryCellularAutomaton.html
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parameter [7 : 0] RULE_2 = 8'b00000010;
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parameter [7 : 0] RULE_2 = 8'b00000010;
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// RULE_90
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// RULE_90
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// This rule generates Pascals triangle from a single
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// This rule generates Pascals triangle from a single
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// bit input. See the following link for more info:
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// bit input. See the following link for more info:
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// http://mathworld.wolfram.com/ElementaryCellularAutomaton.html
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// http://mathworld.wolfram.com/ElementaryCellularAutomaton.html
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parameter [7 : 0] RULE_90 = 8'b01011010;
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parameter [7 : 0] RULE_90 = 8'b01011010;
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// MIDDLE_BIT_INIT_PATTERN
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// MIDDLE_BIT_INIT_PATTERN
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// An initial bgit pattern with a single bit set in the middle
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// An initial bgit pattern with a single bit set in the middle
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// of the 32 bit word.
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// of the 32 bit word.
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parameter [31 : 0] MIDDLE_BIT_INIT_PATTERN = 32'b00000000000000010000000000000000;
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parameter [31 : 0] MIDDLE_BIT_INIT_PATTERN = 32'b00000000000000010000000000000000;
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// COMPLEX_INIT_PATTERN
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// COMPLEX_INIT_PATTERN
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// A more complex init pattern.
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// A more complex init pattern.
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parameter [31 : 0] COMPLEX_INIT_PATTERN = 32'b01011000000000010000111000001100;
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parameter [31 : 0] COMPLEX_INIT_PATTERN = 32'b01011000000000010000111000001100;
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// TC1_RESPONSE
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// TC1_RESPONSE
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// Expected PRNG pattern response after TC1.
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// Expected PRNG pattern response after TC1.
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parameter [31 : 0] TC1_RESPONSE = 32'b01110001010110000000111010001001;
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parameter [31 : 0] TC1_RESPONSE = 32'b01110001010110000000111010001001;
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// TC2_RESPONSE
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// TC2_RESPONSE
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// Expected PRNG pattern response after TC2.
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// Expected PRNG pattern response after TC2.
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parameter [31 : 0] TC2_RESPONSE = 32'b10111101001101000001100001101001;
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parameter [31 : 0] TC2_RESPONSE = 32'b10111101001101000001100001101001;
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// TC3_RESPONSE
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// TC3_RESPONSE
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// Expected PRNG pattern response after TC3.
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// Expected PRNG pattern response after TC3.
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parameter [31 : 0] TC3_RESPONSE = 32'b00000000000000000001000000000000;
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parameter [31 : 0] TC3_RESPONSE = 32'b00000000000000000001000000000000;
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// TC4_RESPONSE
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// TC4_RESPONSE
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// Expected PRNG pattern response after TC4.
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// Expected PRNG pattern response after TC4.
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parameter [31 : 0] TC4_RESPONSE = 32'b10101010101010101010101010101010;
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parameter [31 : 0] TC4_RESPONSE = 32'b10101010101010101010101010101010;
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Wire declarations.
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// Wire declarations.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Wires needed to connect the DUT.
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// Wires needed to connect the DUT.
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reg tb_clk;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_reset_n;
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reg [31 : 0] tb_init_pattern_data;
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reg [31 : 0] tb_init_pattern_data;
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reg tb_load_init_pattern;
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reg tb_load_init_pattern;
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reg tb_next_pattern;
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reg tb_next_pattern;
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reg [7 : 0] tb_update_rule;
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reg [7 : 0] tb_update_rule;
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reg tb_load_update_rule;
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reg tb_load_update_rule;
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wire [31 : 0] tb_prng_data;
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wire [31 : 0] tb_prng_data;
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Testbench variables.
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// Testbench variables.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// num_errors
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// num_errors
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// Number of errors detected.
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// Number of errors detected.
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integer num_errors;
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integer num_errors;
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// ca_prng_dut
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// ca_prng_dut
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//
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//
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// Instantiation of the ca_prng core as device under test.
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// Instantiation of the ca_prng core as device under test.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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ca_prng ca_prng_dut(
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ca_prng ca_prng_dut(
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.clk(tb_clk),
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.reset_n(tb_reset_n),
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|
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.init_pattern_data(tb_init_pattern_data),
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.init_pattern_data(tb_init_pattern_data),
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.load_init_pattern(tb_load_init_pattern),
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.load_init_pattern(tb_load_init_pattern),
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.next_pattern(tb_next_pattern),
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.next_pattern(tb_next_pattern),
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.update_rule(tb_update_rule),
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.update_rule(tb_update_rule),
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.load_update_rule(tb_load_update_rule),
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.load_update_rule(tb_load_update_rule),
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|
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.prng_data(tb_prng_data)
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.prng_data(tb_prng_data)
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// check_pattern
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// check_pattern
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//
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//
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// Check that the reusult pattern matches the expected pattern.
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// Check that the reusult pattern matches the expected pattern.
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// If the patterns don't match increase the error counter.
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// If the patterns don't match increase the error counter.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task check_pattern;
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task check_pattern;
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input [31 : 0] expected_pattern;
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input [31 : 0] expected_pattern;
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input [31 : 0] result_pattern;
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input [31 : 0] result_pattern;
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begin
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begin
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if (expected_pattern != result_pattern)
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if (expected_pattern != result_pattern)
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begin
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begin
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$display("Error: Expected %b, got: %b",
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$display("Error: Expected %b, got: %b",
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expected_pattern, result_pattern);
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expected_pattern, result_pattern);
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num_errors = num_errors + 1;
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num_errors = num_errors + 1;
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end
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end
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end
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end
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endtask // check_pattern
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endtask // check_pattern
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// init_sim
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// init_sim
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//
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//
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// Initialize all DUT inputs variables, testbench variables etc
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// Initialize all DUT inputs variables, testbench variables etc
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// to defined values.
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// to defined values.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task init_sim;
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task init_sim;
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begin
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begin
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tb_clk = 0;
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tb_clk = 0;
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tb_reset_n = 0;
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tb_reset_n = 0;
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tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
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tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
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tb_load_init_pattern = 1'b0;
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tb_load_init_pattern = 1'b0;
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tb_next_pattern = 1'b0;
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tb_next_pattern = 1'b0;
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tb_update_rule = 8'b00000000;
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tb_update_rule = 8'b00000000;
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tb_load_update_rule = 1'b0;
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tb_load_update_rule = 1'b0;
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num_errors = 0;
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num_errors = 0;
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end
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end
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endtask // init_sim
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endtask // init_sim
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// end_sim
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// end_sim
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//
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//
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// Perform any clean up as needed and check the simulation
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// Perform any clean up as needed and check the simulation
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// results from the test cases, reporting number of errors etc.
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// results from the test cases, reporting number of errors etc.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task end_sim;
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task end_sim;
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begin
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begin
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if (num_errors == 0)
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if (num_errors == 0)
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begin
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begin
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$display("Simulation completed ok.");
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$display("Simulation completed ok.");
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end
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end
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else
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else
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begin
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begin
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$display("Simulation completed, but %d test cases had errors.", num_errors);
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$display("Simulation completed, but %d test cases had errors.", num_errors);
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end
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end
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end
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end
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endtask // end_sim
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endtask // end_sim
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// release_reset
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// release_reset
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//
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//
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// Wait a few cycles and then release the reset in sync
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// Wait a few cycles and then release the reset in sync
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// with the clock.
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// with the clock.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task release_reset;
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task release_reset;
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begin
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begin
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#(20 * CLK_HALF_PERIOD);
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#(20 * CLK_HALF_PERIOD);
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_reset_n = 1'b1;
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tb_reset_n = 1'b1;
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end
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end
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endtask // release_reset
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endtask // release_reset
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// test_tc1
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// test_tc1
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//
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//
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// Verify that the default rule30 update rule uns ok from the
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// Verify that the default rule30 update rule uns ok from the
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// start using a simple init pattern.
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// start using a simple init pattern.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task test_tc1;
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task test_tc1;
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begin
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begin
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$display("TC1: Default rule30 update rule with simple init pattern.");
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$display("TC1: Default rule30 update rule with simple init pattern.");
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// Load the init pattern into the dut and then
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// Load the init pattern into the dut and then
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// start asserting the next pattern pin for a while.
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// start asserting the next pattern pin for a while.
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#(4 * CLK_HALF_PERIOD);
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#(4 * CLK_HALF_PERIOD);
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_load_init_pattern = 1'b1;
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tb_load_init_pattern = 1'b1;
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_load_init_pattern = 1'b0;
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tb_load_init_pattern = 1'b0;
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_next_pattern = 1'b1;
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tb_next_pattern = 1'b1;
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// Run the DUT for a number of cycles.
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// Run the DUT for a number of cycles.
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#(100 * CLK_HALF_PERIOD);
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#(100 * CLK_HALF_PERIOD);
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|
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// Drop the next pattern signal and check the results.
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// Drop the next pattern signal and check the results.
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_next_pattern = 1'b0;
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tb_next_pattern = 1'b0;
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check_pattern(TC1_RESPONSE, tb_prng_data);
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check_pattern(TC1_RESPONSE, tb_prng_data);
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end
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end
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endtask // test_tc1
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endtask // test_tc1
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// test_tc2
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// test_tc2
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//
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//
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// Verify that we can change state by changing the init pattern
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// Verify that we can change state by changing the init pattern
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// and get a new set of PRNG data.
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// and get a new set of PRNG data.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task test_tc2;
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task test_tc2;
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begin
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begin
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$display("TC2: Default rule30 update rule with complex init pattern.");
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$display("TC2: Default rule30 update rule with complex init pattern.");
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// Load a new init pattern and run that pattern
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// Load a new init pattern and run that pattern
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_init_pattern_data = COMPLEX_INIT_PATTERN;
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tb_init_pattern_data = COMPLEX_INIT_PATTERN;
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tb_load_init_pattern = 1'b1;
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tb_load_init_pattern = 1'b1;
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_load_init_pattern = 1'b0;
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tb_load_init_pattern = 1'b0;
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tb_next_pattern = 1'b1;
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tb_next_pattern = 1'b1;
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|
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// Run the DUT for a number of cycles.
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// Run the DUT for a number of cycles.
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#(200 * CLK_HALF_PERIOD);
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#(200 * CLK_HALF_PERIOD);
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|
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// Drop the next pattern signal and check the results.
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// Drop the next pattern signal and check the results.
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_next_pattern = 1'b0;
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tb_next_pattern = 1'b0;
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check_pattern(TC2_RESPONSE, tb_prng_data);
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check_pattern(TC2_RESPONSE, tb_prng_data);
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end
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end
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endtask // test_tc2
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endtask // test_tc2
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|
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// test_tc3
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// test_tc3
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//
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//
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// Verify that the we can change the rule and get another set
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// Verify that the we can change the rule and get another set
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// of PRNG data.
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// of PRNG data.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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task test_tc3;
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task test_tc3;
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begin
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begin
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$display("TC3: rule2 update rule with simple init pattern.");
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$display("TC3: rule2 update rule with simple init pattern.");
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// Change update rule to RULE_2 and the simple init pattern.
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// Change update rule to RULE_2 and the simple init pattern.
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_update_rule = RULE_2;
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tb_update_rule = RULE_2;
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tb_load_update_rule = 1'b1;
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tb_load_update_rule = 1'b1;
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tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
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tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
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tb_load_init_pattern = 1'b1;
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tb_load_init_pattern = 1'b1;
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@(negedge tb_clk)
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@(negedge tb_clk)
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tb_load_update_rule = 1'b0;
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tb_load_update_rule = 1'b0;
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tb_load_init_pattern = 1'b0;
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tb_load_init_pattern = 1'b0;
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tb_next_pattern = 1'b1;
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tb_next_pattern = 1'b1;
|
|
|
// Run the DUT for a number of cycles.
|
// Run the DUT for a number of cycles.
|
#(200 * CLK_HALF_PERIOD);
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#(200 * CLK_HALF_PERIOD);
|
|
|
// Drop the next pattern signal and check the results.
|
// Drop the next pattern signal and check the results.
|
@(negedge tb_clk)
|
@(negedge tb_clk)
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tb_next_pattern = 1'b0;
|
tb_next_pattern = 1'b0;
|
check_pattern(TC3_RESPONSE, tb_prng_data);
|
check_pattern(TC3_RESPONSE, tb_prng_data);
|
end
|
end
|
endtask // test_tc3
|
endtask // test_tc3
|
|
|
|
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
// test_tc4
|
// test_tc4
|
//
|
//
|
// Verify that the we can generate Pascals triangle.
|
// Verify that the we can generate Pascals triangle.
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
task test_tc4;
|
task test_tc4;
|
begin
|
begin
|
$display("TC4: rule90 (Pascals triangle) update rule with simple init pattern.");
|
$display("TC4: rule90 (Pascals triangle) update rule with simple init pattern.");
|
// Change update rule to RULE_90 and the simple init pattern.
|
// Change update rule to RULE_90 and the simple init pattern.
|
@(negedge tb_clk)
|
@(negedge tb_clk)
|
tb_update_rule = RULE_90;
|
tb_update_rule = RULE_90;
|
tb_load_update_rule = 1'b1;
|
tb_load_update_rule = 1'b1;
|
tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
|
tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
|
tb_load_init_pattern = 1'b1;
|
tb_load_init_pattern = 1'b1;
|
@(negedge tb_clk)
|
@(negedge tb_clk)
|
tb_load_update_rule = 1'b0;
|
tb_load_update_rule = 1'b0;
|
tb_load_init_pattern = 1'b0;
|
tb_load_init_pattern = 1'b0;
|
tb_next_pattern = 1'b1;
|
tb_next_pattern = 1'b1;
|
|
|
// Run the DUT for a number of cycles.
|
// Run the DUT for a number of cycles.
|
#(30 * CLK_HALF_PERIOD);
|
#(30 * CLK_HALF_PERIOD);
|
|
|
// Drop the next pattern signal and check the results.
|
// Drop the next pattern signal and check the results.
|
@(negedge tb_clk)
|
@(negedge tb_clk)
|
tb_next_pattern = 1'b0;
|
tb_next_pattern = 1'b0;
|
check_pattern(TC4_RESPONSE, tb_prng_data);
|
check_pattern(TC4_RESPONSE, tb_prng_data);
|
end
|
end
|
endtask // test_tc4
|
endtask // test_tc4
|
|
|
|
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
// clk_gen
|
// clk_gen
|
//
|
//
|
// Clock generator process. 50/50 duty cycle.
|
// Clock generator process. 50/50 duty cycle.
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
always
|
always
|
begin : clk_gen
|
begin : clk_gen
|
#CLK_HALF_PERIOD tb_clk = !tb_clk;
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#CLK_HALF_PERIOD tb_clk = !tb_clk;
|
end // clk_gen
|
end // clk_gen
|
|
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
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// dut_monitor
|
// dut_monitor
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//
|
//
|
// Monitor for observing the inputs and outputs to the dut.
|
// Monitor for observing the inputs and outputs to the dut.
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
always @ (posedge tb_clk)
|
always @ (posedge tb_clk)
|
begin : dut_monitor
|
begin : dut_monitor
|
$display("reset = %b, init_pattern = %b, load_init_pattern = %b, next_pattern = %b, prng_data = %b",
|
$display("reset = %b, init_pattern = %b, load_init_pattern = %b, next_pattern = %b, prng_data = %b",
|
tb_reset_n, tb_init_pattern_data, tb_load_init_pattern, tb_next_pattern, tb_prng_data);
|
tb_reset_n, tb_init_pattern_data, tb_load_init_pattern, tb_next_pattern, tb_prng_data);
|
end // dut_monitor
|
end // dut_monitor
|
|
|
|
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
// ca_prng_test
|
// ca_prng_test
|
//
|
//
|
// The main test logic. Basically calls the tasks to init the
|
// The main test logic. Basically calls the tasks to init the
|
// simulation, all test cases and finish the simulation.
|
// simulation, all test cases and finish the simulation.
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
initial
|
initial
|
begin : ca_prng_test
|
begin : ca_prng_test
|
$display(" -- Testbench for for ca_prng module started --");
|
$display(" -- Testbench for for ca_prng module started --");
|
|
|
// Call tasks as needed to init and executing test cases.
|
// Call tasks as needed to init and executing test cases.
|
init_sim;
|
init_sim;
|
release_reset;
|
release_reset;
|
|
|
test_tc1;
|
test_tc1;
|
test_tc2;
|
test_tc2;
|
test_tc3;
|
test_tc3;
|
test_tc4;
|
test_tc4;
|
|
|
end_sim;
|
end_sim;
|
|
|
$display(" -- Testbench for for ca_prng module stopped --");
|
$display(" -- Testbench for for ca_prng module stopped --");
|
$finish;
|
$finish;
|
end // ca_prng_test
|
end // ca_prng_test
|
endmodule // tb_ca_prng
|
endmodule // tb_ca_prng
|
|
|
//========================================================================
|
//========================================================================
|
// EOF tb_ca_prng.v
|
// EOF tb_ca_prng.v
|
//========================================================================
|
//========================================================================
|
|
|
