URL
https://opencores.org/ocsvn/cic_core_2/cic_core_2/trunk
[/] [cic_core_2/] [trunk/] [rtl_sim/] [run/] [cic_d_sim_run.sh] - Diff between revs 5 and 7
Show entire file |
Details |
Blame |
View Log
| Rev 5 |
Rev 7 |
| Line 1... |
Line 1... |
#!/bin/sh
|
#!/bin/sh
|
PATH_CIC=../../../rtl/verilog
|
PATH_CIC=../../rtl/verilog
|
|
mkdir -p ../out
|
iverilog -g2005-sv -g2012 -o ../out/cic_d.out -I $PATH_CIC/ $PATH_CIC/cic_functions.vh $PATH_CIC/cic_d.sv $PATH_CIC/integrator.sv $PATH_CIC/comb.sv $PATH_CIC/downsampler.sv ../src/cic_d_tb.sv || exit # if error then stop
|
iverilog -g2005-sv -g2012 -o ../out/cic_d.out -I $PATH_CIC/ $PATH_CIC/cic_functions.vh $PATH_CIC/cic_d.sv $PATH_CIC/integrator.sv $PATH_CIC/comb.sv $PATH_CIC/downsampler.sv ../src/cic_d_tb.sv || exit # if error then stop
|
echo "iverilog ready, run vvp"
|
echo "iverilog ready, run vvp"
|
vvp ../out/cic_d.out
|
vvp ../out/cic_d.out
|
echo "vvp ready"
|
echo "vvp ready"
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
