-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2009
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Purpose: Clock an asynchronous din into the clk clock domain
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-- Purpose: Clock an asynchronous din into the clk clock domain
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-- Description:
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-- Description:
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-- The delay line combats the potential meta-stability of clocked in data.
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-- The delay line combats the potential meta-stability of clocked in data.
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LIBRARY IEEE, common_pkg_lib;
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY common_async IS
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ENTITY common_async IS
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GENERIC (
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GENERIC (
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g_rising_edge : BOOLEAN := TRUE;
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g_rising_edge : BOOLEAN := TRUE;
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g_rst_level : STD_LOGIC := '0';
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g_rst_level : STD_LOGIC := '0';
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g_delay_len : POSITIVE := c_meta_delay_len -- use common_pipeline if g_delay_len=0 for wires only is also needed
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g_delay_len : POSITIVE := c_meta_delay_len -- use common_pipeline if g_delay_len=0 for wires only is also needed
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC := '0';
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rst : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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din : IN STD_LOGIC;
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din : IN STD_LOGIC;
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dout : OUT STD_LOGIC
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dout : OUT STD_LOGIC
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);
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);
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END;
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END;
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ARCHITECTURE rtl OF common_async IS
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ARCHITECTURE rtl OF common_async IS
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SIGNAL din_meta : STD_LOGIC_VECTOR(0 TO g_delay_len-1) := (OTHERS=>g_rst_level);
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SIGNAL din_meta : STD_LOGIC_VECTOR(0 TO g_delay_len-1) := (OTHERS=>g_rst_level);
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-- Synthesis constraint to ensure that register is kept in this instance region
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-- Synthesis constraint to ensure that register is kept in this instance region
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attribute preserve : boolean;
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attribute preserve : boolean;
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attribute preserve of din_meta : signal is true;
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attribute preserve of din_meta : signal is true;
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BEGIN
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BEGIN
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p_clk : PROCESS (rst, clk)
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p_clk : PROCESS (rst, clk)
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BEGIN
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BEGIN
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IF g_rising_edge=TRUE THEN
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IF g_rising_edge=TRUE THEN
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-- Default use rising edge
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-- Default use rising edge
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IF rst='1' THEN
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IF rst='1' THEN
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din_meta <= (OTHERS=>g_rst_level);
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din_meta <= (OTHERS=>g_rst_level);
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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din_meta <= din & din_meta(0 TO din_meta'HIGH-1);
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din_meta <= din & din_meta(0 TO din_meta'HIGH-1);
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END IF;
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END IF;
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ELSE
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ELSE
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-- also support using falling edge
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-- also support using falling edge
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IF rst='1' THEN
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IF rst='1' THEN
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din_meta <= (OTHERS=>g_rst_level);
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din_meta <= (OTHERS=>g_rst_level);
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ELSIF falling_edge(clk) THEN
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ELSIF falling_edge(clk) THEN
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din_meta <= din & din_meta(0 TO din_meta'HIGH-1);
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din_meta <= din & din_meta(0 TO din_meta'HIGH-1);
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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dout <= din_meta(din_meta'HIGH);
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dout <= din_meta(din_meta'HIGH);
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END rtl;
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END rtl;
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