-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2010
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Purpose: Get in_pulse from in_clk to out_pulse in the out_clk domain.
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-- Purpose: Get in_pulse from in_clk to out_pulse in the out_clk domain.
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-- Description:
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-- Description:
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-- The in_pulse is captured in the in_clk domain and then transfered to the
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-- The in_pulse is captured in the in_clk domain and then transfered to the
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-- out_clk domain. The out_pulse is also only one cycle wide and transfered
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-- out_clk domain. The out_pulse is also only one cycle wide and transfered
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-- back to the in_clk domain to serve as an acknowledge signal to ensure
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-- back to the in_clk domain to serve as an acknowledge signal to ensure
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-- that the in_pulse was recognized also in case the in_clk is faster than
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-- that the in_pulse was recognized also in case the in_clk is faster than
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-- the out_clk. The in_busy is active during the entire transfer. Hence the
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-- the out_clk. The in_busy is active during the entire transfer. Hence the
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-- rate of pulses that can be transfered is limited by g_delay_len and by
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-- rate of pulses that can be transfered is limited by g_delay_len and by
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-- the out_clk rate.
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-- the out_clk rate.
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LIBRARY IEEE, common_pkg_lib;
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY common_spulse IS
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ENTITY common_spulse IS
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GENERIC (
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GENERIC (
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g_delay_len : NATURAL := c_meta_delay_len
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g_delay_len : NATURAL := c_meta_delay_len
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);
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);
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PORT (
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PORT (
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in_rst : IN STD_LOGIC := '0';
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in_rst : IN STD_LOGIC := '0';
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in_clk : IN STD_LOGIC;
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in_clk : IN STD_LOGIC;
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in_clken : IN STD_LOGIC := '1';
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in_clken : IN STD_LOGIC := '1';
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in_pulse : IN STD_LOGIC;
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in_pulse : IN STD_LOGIC;
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in_busy : OUT STD_LOGIC;
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in_busy : OUT STD_LOGIC;
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out_rst : IN STD_LOGIC := '0';
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out_rst : IN STD_LOGIC := '0';
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out_clk : IN STD_LOGIC;
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out_clk : IN STD_LOGIC;
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out_clken : IN STD_LOGIC := '1';
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out_clken : IN STD_LOGIC := '1';
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out_pulse : OUT STD_LOGIC
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out_pulse : OUT STD_LOGIC
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);
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);
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END;
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END;
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ARCHITECTURE rtl OF common_spulse IS
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ARCHITECTURE rtl OF common_spulse IS
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SIGNAL in_level : STD_LOGIC;
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SIGNAL in_level : STD_LOGIC;
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SIGNAL meta_level : STD_LOGIC_VECTOR(0 TO g_delay_len-1);
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SIGNAL meta_level : STD_LOGIC_VECTOR(0 TO g_delay_len-1);
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SIGNAL out_level : STD_LOGIC;
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SIGNAL out_level : STD_LOGIC;
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SIGNAL prev_out_level : STD_LOGIC;
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SIGNAL prev_out_level : STD_LOGIC;
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SIGNAL meta_ack : STD_LOGIC_VECTOR(0 TO g_delay_len-1);
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SIGNAL meta_ack : STD_LOGIC_VECTOR(0 TO g_delay_len-1);
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SIGNAL pulse_ack : STD_LOGIC;
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SIGNAL pulse_ack : STD_LOGIC;
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SIGNAL nxt_out_pulse : STD_LOGIC;
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SIGNAL nxt_out_pulse : STD_LOGIC;
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BEGIN
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BEGIN
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capture_in_pulse : ENTITY work.common_switch
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capture_in_pulse : ENTITY work.common_switch
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PORT MAP (
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PORT MAP (
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clk => in_clk,
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clk => in_clk,
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clken => in_clken,
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clken => in_clken,
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rst => in_rst,
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rst => in_rst,
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switch_high => in_pulse,
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switch_high => in_pulse,
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switch_low => pulse_ack,
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switch_low => pulse_ack,
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out_level => in_level
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out_level => in_level
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);
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);
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in_busy <= in_level OR pulse_ack;
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in_busy <= in_level OR pulse_ack;
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p_out_clk : PROCESS(out_rst, out_clk)
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p_out_clk : PROCESS(out_rst, out_clk)
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BEGIN
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BEGIN
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IF out_rst='1' THEN
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IF out_rst='1' THEN
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meta_level <= (OTHERS=>'0');
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meta_level <= (OTHERS=>'0');
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out_level <= '0';
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out_level <= '0';
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prev_out_level <= '0';
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prev_out_level <= '0';
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out_pulse <= '0';
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out_pulse <= '0';
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ELSIF RISING_EDGE(out_clk) THEN
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ELSIF RISING_EDGE(out_clk) THEN
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IF out_clken='1' THEN
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IF out_clken='1' THEN
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meta_level <= in_level & meta_level(0 TO meta_level'HIGH-1);
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meta_level <= in_level & meta_level(0 TO meta_level'HIGH-1);
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out_level <= meta_level(meta_level'HIGH);
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out_level <= meta_level(meta_level'HIGH);
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prev_out_level <= out_level;
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prev_out_level <= out_level;
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out_pulse <= nxt_out_pulse;
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out_pulse <= nxt_out_pulse;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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p_in_clk : PROCESS(in_rst, in_clk)
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p_in_clk : PROCESS(in_rst, in_clk)
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BEGIN
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BEGIN
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IF in_rst='1' THEN
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IF in_rst='1' THEN
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meta_ack <= (OTHERS=>'0');
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meta_ack <= (OTHERS=>'0');
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pulse_ack <= '0';
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pulse_ack <= '0';
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ELSIF RISING_EDGE(in_clk) THEN
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ELSIF RISING_EDGE(in_clk) THEN
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IF in_clken='1' THEN
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IF in_clken='1' THEN
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meta_ack <= out_level & meta_ack(0 TO meta_ack'HIGH-1);
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meta_ack <= out_level & meta_ack(0 TO meta_ack'HIGH-1);
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pulse_ack <= meta_ack(meta_ack'HIGH);
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pulse_ack <= meta_ack(meta_ack'HIGH);
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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nxt_out_pulse <= out_level AND NOT prev_out_level;
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nxt_out_pulse <= out_level AND NOT prev_out_level;
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END rtl;
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END rtl;
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