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[/] [cop/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 7 and 10

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Rev 7 Rev 10
Line 145... Line 145...
 
 
  // generate clock
  // generate clock
  always #20 mstr_test_clk = ~mstr_test_clk;
  always #20 mstr_test_clk = ~mstr_test_clk;
 
 
  always @(posedge mstr_test_clk)
  always @(posedge mstr_test_clk)
    vector = vector + 1;
    vector <= vector + 1;
 
 
  always @(mstr_test_clk)
  always @(mstr_test_clk)
    begin
    begin
      if (osc_div <= 7)
      if (osc_div <= 7)
        osc_div = osc_div + 1;
        osc_div <= osc_div + 1;
      else
      else
        osc_div = 0;
        osc_div <= 0;
      if (osc_div == 7)
      if (osc_div == 7)
        startup_osc = !startup_osc;
        startup_osc <= !startup_osc;
    end
    end
 
 
  assign osc_clk = startup_osc && en_osc_clk;
  assign osc_clk = startup_osc && en_osc_clk;
 
 
  // hookup wishbone master model
  // hookup wishbone master model

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