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[/] [cop/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 4 and 7

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Rev 4 Rev 7
Line 312... Line 312...
 
 
      cop_count_test;
      cop_count_test;
 
 
      cop_count_test_8;
      cop_count_test_8;
 
 
      $finish;
      cop_irq_test;
 
 
      u0.wb_write(1, SLAVE_0_CNTRL,   COP_CNTRL_DEBUG_ENA); // Enable Slave Mode
 
 
 
      // Set Master Mode PS=0, Modulo=16
 
      test_num = test_num + 1;
 
      $display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
 
 
 
      u0.wb_write(1, COP_TOUT,   16'h0010); // load prescaler hi-byte
 
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); // Enable to start counting
 
      $display("status: %t programmed registers", $time);
 
 
 
      wait_flag_set;  // Wait for Counter to tomeout
 
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_STOP_ENA | COP_CNTRL_COP_ENA); //
 
 
 
      wait_flag_set;  // Wait for Counter to tomeout
 
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_STOP_ENA | COP_CNTRL_COP_ENA); //
 
 
 
      repeat(10) @(posedge mstr_test_clk);
      repeat(10) @(posedge mstr_test_clk);
      u0.wb_write(1, COP_CNTRL, 16'b0); //
 
 
 
      repeat(10) @(posedge mstr_test_clk);
 
 
 
      repeat(100) @(posedge mstr_test_clk);
 
      $display("\nTestbench done at vector=%d\n", vector);
      $display("\nTestbench done at vector=%d\n", vector);
      $finish;
      $finish;
  end
  end
 
 
// Poll for flag set
// Poll for flag set
task wait_flag_set;
task wait_flag_set;
  begin
  begin
    u0.wb_read(1, COP_CNTRL, q);
    u0.wb_read(1, COP_CNTRL, q);
    while(~|(q & COP_CNTRL_STOP_ENA))
    while(~|(q & COP_CNTRL_COP_EVENT))
      u0.wb_read(1, COP_CNTRL, q); // poll it until it is set
      u0.wb_read(1, COP_CNTRL, q); // poll it until it is set
    $display("COP Flag set detected at vector =%d", vector);
    $display("COP Flag set detected at vector =%d", vector);
  end
  end
endtask
endtask
 
 
Line 512... Line 492...
      u0.wb_cmp(  1, COP_CNTRL, COP_CNTRL_COP_ENA); // verify Status bit cleared
      u0.wb_cmp(  1, COP_CNTRL, COP_CNTRL_COP_ENA); // verify Status bit cleared
 
 
   end
   end
endtask
endtask
 
 
 
task cop_irq_test;
 
  begin
 
      test_num = test_num + 1;
 
      $display("TEST #%d Starts at vector=%d, cop_irq_test",
 
                test_num, vector);
 
      // program internal registers
 
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
 
      u0.wb_write(1, COP_TOUT,  16'h0014); // Write TOUT reg
 
//      u0.wb_write(1, COP_CNTRL, COP_CNTRL_IRQ | COP_CNTRL_COP_ENA); //
 
      u0.wb_write(1, COP_CNTRL, 16'h0040 | COP_CNTRL_COP_ENA); //
 
      send_x_osc_clks(10);
 
 
 
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
 
      u0.wb_write(1, COP_TOUT,  16'h0022); // Write TOUT reg
 
      send_x_osc_clks(1);
 
//      u0.wb_write(1, COP_CNTRL, COP_CNTRL_IRQ | COP_CNTRL_COP_ENA); //
 
      u0.wb_write(1, COP_CNTRL, 16'h0080 | COP_CNTRL_COP_ENA); //
 
      send_x_osc_clks(10);
 
   end
 
endtask
 
 
task cop_count_test_8;
task cop_count_test_8;
  begin
  begin
      test_num = test_num + 1;
      test_num = test_num + 1;
      $display("TEST #%d Starts at vector=%d, cop_count_test_8",
      $display("TEST #%d Starts at vector=%d, cop_count_test_8",
                test_num, vector);
                test_num, vector);

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