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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [descrambler_tb.vhd] - Diff between revs 6 and 9

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Rev 6 Rev 9
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entity testbench_descrambler is
entity testbench_descrambler is
end entity testbench_descrambler;
end entity testbench_descrambler;
 
 
architecture tb_descrambler of testbench_descrambler is
architecture tb_descrambler of testbench_descrambler is
 
 
    signal Clk          : std_logic;                     -- Clock input
    signal Clk          : std_logic;                     -- Interface clock
        signal Reset            : std_logic;                                     -- Reset decoder
        signal Reset            : std_logic;                                     -- Descrambler reset, use for initialization
 
 
        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
        signal Data_Out     : std_logic_vector(63 downto 0); -- Decoded 64-bit output
        signal Data_Out     : std_logic_vector(63 downto 0); -- Data output
        signal Data_Control_In : std_logic;                    --       Indicates whether the word is data or control
 
        signal Data_Control_Out : std_logic;                    --      Indicates whether the word is data or control
        signal Lane_Number      : std_logic_vector (3 downto 0); -- Each lane number starts with different scrambler word
        signal Lane_Number     : std_logic_vector (3 downto 0);
        signal Data_Control_In  : std_logic;                    --      Indicates a control word
 
        signal Data_Control_Out : std_logic;                    -- Output control word indication
 
    signal Data_Valid_In    : std_logic;                    -- Only valid data will be processed
 
    signal Data_Valid_Out   : std_logic;
 
    signal Lock             : std_logic;
 
 
        signal Error_BadSync            : std_logic;
        signal Error_BadSync            : std_logic;
        signal Error_StateMismatch      : std_logic;
        signal Error_StateMismatch      : std_logic;
        signal Error_NoSync                     : std_logic;
        signal Error_NoSync                     : std_logic;
        signal Data_Valid_Out  : std_logic;
 
 
 
 
 
 constant CLK_PERIOD : time := 10 ns;
 constant CLK_PERIOD : time := 10 ns;
 
 
begin
begin
  uut : entity work.Descrambler
  uut : entity work.Descrambler
Line 27... Line 31...
    clk => clk,
    clk => clk,
    reset => reset,
    reset => reset,
 
 
    Data_in => Data_in,
    Data_in => Data_in,
    Data_out => Data_out,
    Data_out => Data_out,
 
 
 
        Lane_Number => Lane_Number,
    Data_control_In => Data_control_In,
    Data_control_In => Data_control_In,
    Data_control_Out => Data_control_Out,
    Data_control_Out => Data_control_Out,
 
        Data_valid_in  => Data_valid_in,
    Data_valid_out => Data_valid_out,
    Data_valid_out => Data_valid_out,
 
        Lock           => Lock,
    Lane_Number => Lane_Number,
 
 
 
    Error_BadSync => Error_BadSync,
    Error_BadSync => Error_BadSync,
    Error_StateMismatch => Error_StateMismatch,
    Error_StateMismatch => Error_StateMismatch,
        Error_NoSync => Error_NoSync
        Error_NoSync => Error_NoSync
  );
  );

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