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entity testbench_meta is
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entity testbench_meta is
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end entity testbench_meta;
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end entity testbench_meta;
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architecture tb_meta of testbench_meta is
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architecture tb_meta of testbench_meta is
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signal clk : std_logic;
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signal clk : std_logic; -- System clock
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signal reset : std_logic;
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signal reset : std_logic; -- Reset, use for initialization.
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signal TX_Enable : std_logic;
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signal TX_Enable : std_logic;
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signal HealthLane : std_logic := '0';
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signal HealthInterface : std_logic := '0';
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signal Data_in : std_logic_vector(63 downto 0); -- Input data
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signal HealthLane : std_logic; -- Lane status bit transmitted in diagnostic
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signal Data_out : std_logic_vector(63 downto 0); -- To scrambling/framing
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signal HealthInterface : std_logic; -- Interface status bit transmitted in diagnostic
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signal Data_valid_in : std_logic; -- Indicate data transmitted is valid
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signal Data_valid_out : std_logic; -- Indicate data transmitted is valid
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signal Data_Control_In : std_logic;
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signal Data_control_out : std_logic; -- Control word indication
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signal Gearboxready : std_logic;
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signal Data_In : std_logic_vector(63 downto 0); -- Input data
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signal Data_Out : std_logic_vector(63 downto 0); -- To scrambling/framing
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signal Data_Valid_In : std_logic; -- Indicate data received is valid
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signal Data_Valid_Out : std_logic; -- Indicate data transmitted is valid
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signal Data_Control_In : std_logic; -- Control word indication from the burst component
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signal Data_Control_Out : std_logic; -- Control word indication
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signal FIFO_read : std_logic; -- Request data from the FIFO
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signal Gearboxready : std_logic;
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signal FIFO_read : std_logic;
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : entity work.metaframing
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uut : entity work.Meta_Framer
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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TX_Enable => TX_Enable,
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TX_Enable => TX_Enable,
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HealthLane => HealthLane,
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HealthLane => HealthLane,
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HealthInterface => HealthInterface,
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HealthInterface => HealthInterface,
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Data_in => Data_in,
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Data_in => Data_in,
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Data_out => Data_out,
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Data_out => Data_out,
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Data_valid_in => Data_valid_in,
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Data_valid_in => Data_valid_in,
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Data_valid_out => Data_valid_out,
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Data_valid_out => Data_valid_out,
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Data_control_in => Data_control_in,
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Data_control_in => Data_control_in,
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Data_control_out => Data_control_out,
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Data_control_out => Data_control_out,
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Gearboxready => Gearboxready,
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Gearboxready => Gearboxready,
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FIFO_read => FIFO_read
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FIFO_read => FIFO_read
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);
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);
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Clk_process :process
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Clk_process :process
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