URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [TO_DO_list.txt] - Diff between revs 24 and 26

Rev 24	Rev 26
Line 1...	Line 1...
	`(September 15th 2018)`
	`- (WORKING) Performance improvements`
	`- (WORKING) Creating test strategy for RDY signal`
	`- (DONE) Working on reported Bugs/Requests: Branches, Interrupts, ADC/SBC`
	`- (DONE) Verifying all interrupts`
	`- (90%) Finish working for Specification of cpu65C02_tc`

`(March 15th 2010)`	`(March 15th 2010)`
`- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by`	`- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by`
`simulation with RTI and in a real environment by customer.`	`simulation with RTI and in a real environment by customer.`
`- (DONE) Removed directory ./verilog_TRIAL from source.`	`- (DONE) Removed directory ./verilog_TRIAL from source.`
`- (DONE) Updated HTML`	`- (DONE) Updated HTML`