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(September 15th 2018)
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- (WORKING) Performance improvements
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- (WORKING) Creating test strategy for RDY signal
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- (DONE) Working on reported Bugs/Requests: Branches, Interrupts, ADC/SBC
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- (DONE) Verifying all interrupts
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- (90%) Finish working for Specification of cpu65C02_tc
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(March 15th 2010)
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(March 15th 2010)
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- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by
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- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by
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simulation with RTI and in a real environment by customer.
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simulation with RTI and in a real environment by customer.
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- (DONE) Removed directory ./verilog_TRIAL from source.
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- (DONE) Removed directory ./verilog_TRIAL from source.
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- (DONE) Updated HTML
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- (DONE) Updated HTML
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(February 25th 2009)
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(February 25th 2009)
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- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
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- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
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- (DONE) RENAME all states of "FSM Execution Unit" for better reading
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- (DONE) RENAME all states of "FSM Execution Unit" for better reading
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- (90%) Finish working for Specification of cpu6502_tc
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- (90%) Finish working for Specification of cpu6502_tc
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(January, 4th 2009)
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(January, 4th 2009)
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- (DONE) Remove unused nets, register and modules
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- (DONE) Remove unused nets, register and modules
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- (85%) Finish working for Specification of cpu65C02_tc
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- (85%) Finish working for Specification of cpu65C02_tc
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- (DONE) Update the HDL Designer files for better viewing and
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- (DONE) Update the HDL Designer files for better viewing and
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understanding
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understanding
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(August, 5th 2008)
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(August, 5th 2008)
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- (DONE) Rename all port names (_i, _o, _o_i)
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- (DONE) Rename all port names (_i, _o, _o_i)
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- (DONE) Test and verify all Op Codes
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- (DONE) Test and verify all Op Codes
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- (DONE) Optimize core for speed
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- (DONE) Optimize core for speed
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- (75%) Finish working for Specification of cpu65C02_tc
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- (75%) Finish working for Specification of cpu65C02_tc
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- (WORKING) Create high level testbench in assembler and hardware for
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- (WORKING) Create high level testbench in assembler and hardware for
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testing all Op Codes (include accurate cycle timing)
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testing all Op Codes (include accurate cycle timing)
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- (WORKING) Create simulation files for Modelsim
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- (WORKING) Create simulation files for Modelsim
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- (WORKING) Create a simple .wlf file to demonstrate the cpu6502_tc
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- (WORKING) Create a simple .wlf file to demonstrate the cpu6502_tc
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