OpenCores
URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [doc/] [errata.txt] - Diff between revs 25 and 26

Only display areas with differences | Details | Blame | View Log

Rev 25 Rev 26
v1.11 BETA 2013/07/24
v1.4 2018/09/15
 
FUNCTIONALITY:
 
 no errata reported/opened
 
 
 
TIMING:
 
 no errata reported/opened
 
 
 
SIGNALING:
 
 no errata reported/opened
 
 
 
 
 
v1.4 BETA 2013/07/24
FUNCTIONALITY:
FUNCTIONALITY:
- ADC and SBC in decimal mode (all op codes -
- ADC and SBC in decimal mode (all op codes -
  seems to use a formula different from a real R6502.
  seems to use a formula different from a real R6502.
TIMING:
TIMING:
- All Branch Instructions
- All Branch Instructions
  (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
  (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
  4 cycles if branch forward occur and the branch
  4 cycles if branch forward occur and the branch
  instruction lies on a xxFEh location.
  instruction lies on a xxFEh location.
  Must be 3 cycles.
  Must be 3 cycles.
SIGNALING:
SIGNALING:
- Hardware Interrupts NMI & IRQ - NO "SYNC"
- Hardware Interrupts NMI & IRQ - NO "SYNC"
- RESET generates NO SYNC
- RESET generates NO SYNC
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.