| Line 1... |
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-- VHDL Entity R6502_TC.Core.symbol
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-- VHDL Entity r6502_tc.core.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 14:13:52 08.03.2010
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-- at - 09:42:07 11.09.2018
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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ENTITY Core IS
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entity core is
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PORT(
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port(
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clk_clk_i : IN std_logic;
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clk_clk_i : in std_logic;
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d_i : IN std_logic_vector (7 DOWNTO 0);
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d_i : in std_logic_vector (7 downto 0);
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irq_n_i : IN std_logic;
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irq_n_i : in std_logic;
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nmi_n_i : IN std_logic;
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nmi_n_i : in std_logic;
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rdy_i : IN std_logic;
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rdy_i : in std_logic;
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rst_rst_n_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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so_n_i : IN std_logic;
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so_n_i : in std_logic;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
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a_o : out std_logic_vector (15 downto 0);
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d_o : OUT std_logic_vector (7 DOWNTO 0);
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d_o : out std_logic_vector (7 downto 0);
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rd_o : OUT std_logic;
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rd_o : out std_logic;
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sync_o : OUT std_logic;
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sync_o : out std_logic;
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wr_n_o : OUT std_logic;
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wr_n_o : out std_logic;
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wr_o : OUT std_logic
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wr_o : out std_logic
|
);
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);
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-- Declarations
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-- Declarations
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|
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END Core ;
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end core ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- scantara2003@yahoo.de
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-- (email: opencores@vivare-services.com)
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
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-- Versions:
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-- 3 of the License, or any later version.
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-- Revision 1.20 2013/07/24 11:11:00 jens
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-- - Changing the title block and internal revision history
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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-- Revision 1.6 2009/01/04 10:20:47 eda
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-- PARTICULAR PURPOSE. See the GNU General Public License for more details.
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-- Changes for cosmetic issues only
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--
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- Revision 1.5 2009/01/04 09:23:10 eda
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-- - Delete unused nets and blocks
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-- - Rename blocks
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--
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-- Revision 1.4 2009/01/03 16:53:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.3 2009/01/03 16:42:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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--
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-- CVS Revisins History
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-- Revision 1.2 2008/12/31 19:31:24 eda
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-- Production Release
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--
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--
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-- $Log: struct.bd,v $
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-- <<-- more -->>
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-- Title: Core
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-- Path: R6502_TC/Core/struct
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-- Edited: by eda on 08 Feb 2010
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--
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--
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-- VHDL Architecture R6502_TC.Core.struct
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--
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-- VHDL Architecture r6502_tc.core.struct
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--
|
--
|
-- Created:
|
-- Created:
|
-- by - eda.UNKNOWN (ENTW1)
|
-- by - eda.UNKNOWN (ENTW-7HPZ200)
|
-- at - 14:13:53 08.03.2010
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-- at - 11:46:25 11.09.2018
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|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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|
--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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LIBRARY R6502_TC;
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library r6502_tc;
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|
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ARCHITECTURE struct OF Core IS
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architecture struct of core is
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);
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signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
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SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0);
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signal adr_o_i : std_logic_vector(15 downto 0);
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SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
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signal adr_pc_o_i : std_logic_vector(15 downto 0);
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SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0);
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signal adr_sp_o_i : std_logic_vector(15 downto 0);
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SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0);
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signal ch_a_o_i : std_logic_vector(7 downto 0);
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SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0);
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signal ch_b_o_i : std_logic_vector(7 downto 0);
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SIGNAL d_alu_n_o_i : std_logic;
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signal d_alu_n_o_i : std_logic;
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SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0);
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signal d_alu_o_i : std_logic_vector(7 downto 0);
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SIGNAL d_alu_or_o_i : std_logic;
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signal d_alu_or_o_i : std_logic;
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SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0);
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signal d_regs_in_o_i : std_logic_vector(7 downto 0);
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SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);
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signal d_regs_out_o_i : std_logic_vector(7 downto 0);
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SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0);
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signal ld_o_i : std_logic_vector(1 downto 0);
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SIGNAL ld_pc_o_i : std_logic;
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signal ld_pc_o_i : std_logic;
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SIGNAL ld_sp_o_i : std_logic;
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signal ld_sp_o_i : std_logic;
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SIGNAL load_regs_o_i : std_logic;
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signal load_regs_o_i : std_logic;
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SIGNAL nmi_o_i : std_logic;
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signal nmi_o_i : std_logic;
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SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0);
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signal offset_o_i : std_logic_vector(15 downto 0);
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SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0);
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signal q_a_o_i : std_logic_vector(7 downto 0);
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SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0);
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signal q_x_o_i : std_logic_vector(7 downto 0);
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SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0);
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signal q_y_o_i : std_logic_vector(7 downto 0);
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SIGNAL reg_0flag_o_i : std_logic;
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signal reg_0flag_o_i : std_logic;
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SIGNAL reg_1flag_o_i : std_logic;
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signal reg_1flag_o_i : std_logic;
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SIGNAL reg_7flag_o_i : std_logic;
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signal reg_7flag_o_i : std_logic;
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SIGNAL rst_nmi_o_i : std_logic;
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signal rst_nmi_o_i : std_logic;
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SIGNAL sel_pc_in_o_i : std_logic;
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signal sel_pc_in_o_i : std_logic;
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SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);
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signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
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SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0);
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signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
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SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);
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signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
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SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0);
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signal sel_reg_o_i : std_logic_vector(1 downto 0);
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SIGNAL sel_sp_as_o_i : std_logic;
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signal sel_sp_as_o_i : std_logic;
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SIGNAL sel_sp_in_o_i : std_logic;
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signal sel_sp_in_o_i : std_logic;
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|
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|
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-- Component Declarations
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-- Component Declarations
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COMPONENT FSM_Execution_Unit
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component fsm_execution_unit
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PORT (
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port (
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adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
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adr_nxt_pc_i : in std_logic_vector (15 downto 0);
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adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
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adr_pc_i : in std_logic_vector (15 downto 0);
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adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
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adr_sp_i : in std_logic_vector (15 downto 0);
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clk_clk_i : IN std_logic ;
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clk_clk_i : in std_logic ;
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d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
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d_alu_i : in std_logic_vector ( 7 downto 0 );
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d_i : IN std_logic_vector ( 7 DOWNTO 0 );
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d_i : in std_logic_vector ( 7 downto 0 );
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d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
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d_regs_out_i : in std_logic_vector ( 7 downto 0 );
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irq_n_i : IN std_logic ;
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irq_n_i : in std_logic ;
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nmi_i : IN std_logic ;
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nmi_i : in std_logic ;
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q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
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q_a_i : in std_logic_vector ( 7 downto 0 );
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q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
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q_x_i : in std_logic_vector ( 7 downto 0 );
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q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
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q_y_i : in std_logic_vector ( 7 downto 0 );
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rdy_i : IN std_logic ;
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rdy_i : in std_logic ;
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reg_0flag_i : IN std_logic ;
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reg_0flag_i : in std_logic ;
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reg_1flag_i : IN std_logic ;
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reg_1flag_i : in std_logic ;
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reg_7flag_i : IN std_logic ;
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reg_7flag_i : in std_logic ;
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rst_rst_n_i : IN std_logic ;
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rst_rst_n_i : in std_logic ;
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so_n_i : IN std_logic ;
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so_n_i : in std_logic ;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
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a_o : out std_logic_vector (15 downto 0);
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adr_o : OUT std_logic_vector (15 DOWNTO 0);
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adr_o : out std_logic_vector (15 downto 0);
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ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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ch_a_o : out std_logic_vector ( 7 downto 0 );
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ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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ch_b_o : out std_logic_vector ( 7 downto 0 );
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d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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d_o : out std_logic_vector ( 7 downto 0 );
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d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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d_regs_in_o : out std_logic_vector ( 7 downto 0 );
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ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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int_fetch_o : out std_logic ;
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ld_pc_o : OUT std_logic ;
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int_reg_2flag_o : out std_logic ;
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ld_sp_o : OUT std_logic ;
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ld_o : out std_logic_vector ( 1 downto 0 );
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load_regs_o : OUT std_logic ;
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ld_pc_o : out std_logic ;
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offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
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ld_sp_o : out std_logic ;
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rd_o : OUT std_logic ;
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load_regs_o : out std_logic ;
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rst_nmi_o : OUT std_logic ;
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offset_o : out std_logic_vector ( 15 downto 0 );
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sel_pc_in_o : OUT std_logic ;
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rd_o : out std_logic ;
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sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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rst_nmi_o : out std_logic ;
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sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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sel_pc_in_o : out std_logic ;
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sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
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sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
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sel_sp_as_o : OUT std_logic ;
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sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
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sel_sp_in_o : OUT std_logic ;
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sel_reg_o : out std_logic_vector ( 1 downto 0 );
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sync_o : OUT std_logic ;
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sel_sp_as_o : out std_logic ;
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wr_n_o : OUT std_logic ;
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sel_sp_in_o : out std_logic ;
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wr_o : OUT std_logic
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sync_o : out std_logic ;
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);
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wr_n_o : out std_logic ;
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END COMPONENT;
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wr_o : out std_logic
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COMPONENT FSM_NMI
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);
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PORT (
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end component;
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clk_clk_i : IN std_logic ;
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component fsm_intnmi
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nmi_n_i : IN std_logic ;
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port (
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rst_nmi_i : IN std_logic ;
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clk_clk_i : in std_logic ;
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rst_rst_n_i : IN std_logic ;
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nmi_n_i : in std_logic ;
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nmi_o : OUT std_logic
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rst_nmi_i : in std_logic ;
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);
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rst_rst_n_i : in std_logic ;
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END COMPONENT;
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nmi_o : out std_logic
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COMPONENT RegBank_AXY
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);
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PORT (
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end component;
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clk_clk_i : IN std_logic ;
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component reg_pc
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d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
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port (
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load_regs_i : IN std_logic ;
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adr_i : in std_logic_vector (15 downto 0);
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rst_rst_n_i : IN std_logic ;
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clk_clk_i : in std_logic ;
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sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
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ld_i : in std_logic_vector (1 downto 0);
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sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
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ld_pc_i : in std_logic ;
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sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
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offset_i : in std_logic_vector (15 downto 0);
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d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
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rst_rst_n_i : in std_logic ;
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q_a_o : OUT std_logic_vector (7 DOWNTO 0);
|
sel_pc_in_i : in std_logic ;
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q_x_o : OUT std_logic_vector (7 DOWNTO 0);
|
sel_pc_val_i : in std_logic_vector (1 downto 0);
|
q_y_o : OUT std_logic_vector (7 DOWNTO 0)
|
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
|
);
|
adr_pc_o : out std_logic_vector (15 downto 0)
|
END COMPONENT;
|
);
|
COMPONENT Reg_PC
|
end component;
|
PORT (
|
component reg_sp
|
adr_i : IN std_logic_vector (15 DOWNTO 0);
|
port (
|
clk_clk_i : IN std_logic ;
|
adr_low_i : in std_logic_vector (7 downto 0);
|
ld_i : IN std_logic_vector (1 DOWNTO 0);
|
clk_clk_i : in std_logic ;
|
ld_pc_i : IN std_logic ;
|
ld_low_i : in std_logic ;
|
offset_i : IN std_logic_vector (15 DOWNTO 0);
|
ld_sp_i : in std_logic ;
|
rst_rst_n_i : IN std_logic ;
|
rst_rst_n_i : in std_logic ;
|
sel_pc_in_i : IN std_logic ;
|
sel_sp_as_i : in std_logic ;
|
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
|
sel_sp_in_i : in std_logic ;
|
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
|
adr_sp_o : out std_logic_vector (15 downto 0)
|
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
|
);
|
);
|
end component;
|
END COMPONENT;
|
component regbank_axy
|
COMPONENT Reg_SP
|
port (
|
PORT (
|
clk_clk_i : in std_logic ;
|
adr_low_i : IN std_logic_vector (7 DOWNTO 0);
|
d_regs_in_i : in std_logic_vector (7 downto 0);
|
clk_clk_i : IN std_logic ;
|
load_regs_i : in std_logic ;
|
ld_low_i : IN std_logic ;
|
rst_rst_n_i : in std_logic ;
|
ld_sp_i : IN std_logic ;
|
sel_rb_in_i : in std_logic_vector (1 downto 0);
|
rst_rst_n_i : IN std_logic ;
|
sel_rb_out_i : in std_logic_vector (1 downto 0);
|
sel_sp_as_i : IN std_logic ;
|
sel_reg_i : in std_logic_vector (1 downto 0);
|
sel_sp_in_i : IN std_logic ;
|
d_regs_out_o : out std_logic_vector (7 downto 0);
|
adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)
|
q_a_o : out std_logic_vector (7 downto 0);
|
|
q_x_o : out std_logic_vector (7 downto 0);
|
|
q_y_o : out std_logic_vector (7 downto 0)
|
);
|
);
|
END COMPONENT;
|
end component;
|
|
|
-- Optional embedded configurations
|
-- Optional embedded configurations
|
-- pragma synthesis_off
|
-- pragma synthesis_off
|
FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit;
|
for all : fsm_execution_unit use entity r6502_tc.fsm_execution_unit;
|
FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI;
|
for all : fsm_intnmi use entity r6502_tc.fsm_intnmi;
|
FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY;
|
for all : reg_pc use entity r6502_tc.reg_pc;
|
FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC;
|
for all : reg_sp use entity r6502_tc.reg_sp;
|
FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP;
|
for all : regbank_axy use entity r6502_tc.regbank_axy;
|
-- pragma synthesis_on
|
-- pragma synthesis_on
|
|
|
|
|
BEGIN
|
begin
|
|
|
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
|
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
|
u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)
|
u_11combo_proc: process (ch_a_o_i, ch_b_o_i)
|
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
|
variable temp_din0 : std_logic_vector(8 downto 0);
|
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
|
variable temp_din1 : std_logic_vector(8 downto 0);
|
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
|
variable temp_sum : unsigned(8 downto 0);
|
VARIABLE temp_carry : std_logic;
|
variable temp_carry : std_logic;
|
BEGIN
|
begin
|
temp_din0 := '0' & ch_a_o_i;
|
temp_din0 := '0' & ch_a_o_i;
|
temp_din1 := '0' & ch_b_o_i;
|
temp_din1 := '0' & ch_b_o_i;
|
temp_carry := '0';
|
temp_carry := '0';
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
|
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
|
reg_0flag_o_i <= temp_sum(8) ;
|
reg_0flag_o_i <= temp_sum(8) ;
|
END PROCESS u_11combo_proc;
|
end process u_11combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
|
-- ModuleWare code(v1.12) for instance 'U_8' of 'inv'
|
reg_1flag_o_i <= NOT(d_alu_or_o_i);
|
reg_1flag_o_i <= not(d_alu_or_o_i);
|
|
|
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
|
-- ModuleWare code(v1.12) for instance 'U_9' of 'inv'
|
reg_7flag_o_i <= NOT(d_alu_n_o_i);
|
reg_7flag_o_i <= not(d_alu_n_o_i);
|
|
|
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
|
-- ModuleWare code(v1.12) for instance 'U_10' of 'inv'
|
d_alu_n_o_i <= NOT(d_alu_o_i(7));
|
d_alu_n_o_i <= not(d_alu_o_i(7));
|
|
|
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
|
-- ModuleWare code(v1.12) for instance 'U_7' of 'por'
|
d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7);
|
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
|
|
|
-- Instance port mappings.
|
-- Instance port mappings.
|
U_4 : FSM_Execution_Unit
|
U_4 : fsm_execution_unit
|
PORT MAP (
|
port map (
|
adr_nxt_pc_i => adr_nxt_pc_o_i,
|
adr_nxt_pc_i => adr_nxt_pc_o_i,
|
adr_pc_i => adr_pc_o_i,
|
adr_pc_i => adr_pc_o_i,
|
adr_sp_i => adr_sp_o_i,
|
adr_sp_i => adr_sp_o_i,
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
d_alu_i => d_alu_o_i,
|
d_alu_i => d_alu_o_i,
|
| Line 264... |
Line 282... |
adr_o => adr_o_i,
|
adr_o => adr_o_i,
|
ch_a_o => ch_a_o_i,
|
ch_a_o => ch_a_o_i,
|
ch_b_o => ch_b_o_i,
|
ch_b_o => ch_b_o_i,
|
d_o => d_o,
|
d_o => d_o,
|
d_regs_in_o => d_regs_in_o_i,
|
d_regs_in_o => d_regs_in_o_i,
|
|
int_fetch_o => open,
|
|
int_reg_2flag_o => open,
|
ld_o => ld_o_i,
|
ld_o => ld_o_i,
|
ld_pc_o => ld_pc_o_i,
|
ld_pc_o => ld_pc_o_i,
|
ld_sp_o => ld_sp_o_i,
|
ld_sp_o => ld_sp_o_i,
|
load_regs_o => load_regs_o_i,
|
load_regs_o => load_regs_o_i,
|
offset_o => offset_o_i,
|
offset_o => offset_o_i,
|
| Line 282... |
Line 302... |
sel_sp_in_o => sel_sp_in_o_i,
|
sel_sp_in_o => sel_sp_in_o_i,
|
sync_o => sync_o,
|
sync_o => sync_o,
|
wr_n_o => wr_n_o,
|
wr_n_o => wr_n_o,
|
wr_o => wr_o
|
wr_o => wr_o
|
);
|
);
|
U_6 : FSM_NMI
|
U_6 : fsm_intnmi
|
PORT MAP (
|
port map (
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
nmi_n_i => nmi_n_i,
|
nmi_n_i => nmi_n_i,
|
rst_nmi_i => rst_nmi_o_i,
|
rst_nmi_i => rst_nmi_o_i,
|
rst_rst_n_i => rst_rst_n_i,
|
rst_rst_n_i => rst_rst_n_i,
|
nmi_o => nmi_o_i
|
nmi_o => nmi_o_i
|
);
|
);
|
U_2 : RegBank_AXY
|
U_0 : reg_pc
|
PORT MAP (
|
port map (
|
clk_clk_i => clk_clk_i,
|
|
d_regs_in_i => d_regs_in_o_i,
|
|
load_regs_i => load_regs_o_i,
|
|
rst_rst_n_i => rst_rst_n_i,
|
|
sel_rb_in_i => sel_rb_in_o_i,
|
|
sel_rb_out_i => sel_rb_out_o_i,
|
|
sel_reg_i => sel_reg_o_i,
|
|
d_regs_out_o => d_regs_out_o_i,
|
|
q_a_o => q_a_o_i,
|
|
q_x_o => q_x_o_i,
|
|
q_y_o => q_y_o_i
|
|
);
|
|
U_0 : Reg_PC
|
|
PORT MAP (
|
|
adr_i => adr_o_i,
|
adr_i => adr_o_i,
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
ld_i => ld_o_i,
|
ld_i => ld_o_i,
|
ld_pc_i => ld_pc_o_i,
|
ld_pc_i => ld_pc_o_i,
|
offset_i => offset_o_i,
|
offset_i => offset_o_i,
|
| Line 317... |
Line 323... |
sel_pc_in_i => sel_pc_in_o_i,
|
sel_pc_in_i => sel_pc_in_o_i,
|
sel_pc_val_i => sel_pc_val_o_i,
|
sel_pc_val_i => sel_pc_val_o_i,
|
adr_nxt_pc_o => adr_nxt_pc_o_i,
|
adr_nxt_pc_o => adr_nxt_pc_o_i,
|
adr_pc_o => adr_pc_o_i
|
adr_pc_o => adr_pc_o_i
|
);
|
);
|
U_1 : Reg_SP
|
U_1 : reg_sp
|
PORT MAP (
|
port map (
|
adr_low_i => adr_o_i(7 DOWNTO 0),
|
adr_low_i => adr_o_i(7 DOWNTO 0),
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
ld_low_i => ld_o_i(0),
|
ld_low_i => ld_o_i(0),
|
ld_sp_i => ld_sp_o_i,
|
ld_sp_i => ld_sp_o_i,
|
rst_rst_n_i => rst_rst_n_i,
|
rst_rst_n_i => rst_rst_n_i,
|
sel_sp_as_i => sel_sp_as_o_i,
|
sel_sp_as_i => sel_sp_as_o_i,
|
sel_sp_in_i => sel_sp_in_o_i,
|
sel_sp_in_i => sel_sp_in_o_i,
|
adr_sp_o => adr_sp_o_i
|
adr_sp_o => adr_sp_o_i
|
);
|
);
|
|
U_2 : regbank_axy
|
|
port map (
|
|
clk_clk_i => clk_clk_i,
|
|
d_regs_in_i => d_regs_in_o_i,
|
|
load_regs_i => load_regs_o_i,
|
|
rst_rst_n_i => rst_rst_n_i,
|
|
sel_rb_in_i => sel_rb_in_o_i,
|
|
sel_rb_out_i => sel_rb_out_o_i,
|
|
sel_reg_i => sel_reg_o_i,
|
|
d_regs_out_o => d_regs_out_o_i,
|
|
q_a_o => q_a_o_i,
|
|
q_x_o => q_x_o_i,
|
|
q_y_o => q_y_o_i
|
|
);
|
|
|
END struct;
|
end struct;
|
|
|
No newline at end of file
|
No newline at end of file
|
