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-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
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-- VHDL Entity r6502_tc.fsm_execution_unit.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 15:57:20 20.02.2010
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-- at - 11:35:43 11.09.2018
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FSM_Execution_Unit IS
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entity fsm_execution_unit is
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PORT(
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port(
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adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
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adr_nxt_pc_i : in std_logic_vector (15 downto 0);
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adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
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adr_pc_i : in std_logic_vector (15 downto 0);
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adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
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adr_sp_i : in std_logic_vector (15 downto 0);
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clk_clk_i : IN std_logic;
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clk_clk_i : in std_logic;
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d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
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d_alu_i : in std_logic_vector ( 7 downto 0 );
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d_i : IN std_logic_vector ( 7 DOWNTO 0 );
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d_i : in std_logic_vector ( 7 downto 0 );
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d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
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d_regs_out_i : in std_logic_vector ( 7 downto 0 );
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irq_n_i : IN std_logic;
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irq_n_i : in std_logic;
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nmi_i : IN std_logic;
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nmi_i : in std_logic;
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q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
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q_a_i : in std_logic_vector ( 7 downto 0 );
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q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
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q_x_i : in std_logic_vector ( 7 downto 0 );
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q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
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q_y_i : in std_logic_vector ( 7 downto 0 );
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rdy_i : IN std_logic;
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rdy_i : in std_logic;
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reg_0flag_i : IN std_logic;
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reg_0flag_i : in std_logic;
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reg_1flag_i : IN std_logic;
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reg_1flag_i : in std_logic;
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reg_7flag_i : IN std_logic;
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reg_7flag_i : in std_logic;
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rst_rst_n_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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so_n_i : IN std_logic;
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so_n_i : in std_logic;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
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a_o : out std_logic_vector (15 downto 0);
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adr_o : OUT std_logic_vector (15 DOWNTO 0);
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adr_o : out std_logic_vector (15 downto 0);
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ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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ch_a_o : out std_logic_vector ( 7 downto 0 );
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ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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ch_b_o : out std_logic_vector ( 7 downto 0 );
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d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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d_o : out std_logic_vector ( 7 downto 0 );
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d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
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d_regs_in_o : out std_logic_vector ( 7 downto 0 );
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ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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int_fetch_o : out std_logic;
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ld_pc_o : OUT std_logic;
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int_reg_2flag_o : out std_logic;
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ld_sp_o : OUT std_logic;
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ld_o : out std_logic_vector ( 1 downto 0 );
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load_regs_o : OUT std_logic;
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ld_pc_o : out std_logic;
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offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
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ld_sp_o : out std_logic;
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rd_o : OUT std_logic;
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load_regs_o : out std_logic;
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rst_nmi_o : OUT std_logic;
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offset_o : out std_logic_vector ( 15 downto 0 );
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sel_pc_in_o : OUT std_logic;
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rd_o : out std_logic;
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sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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rst_nmi_o : out std_logic;
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sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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sel_pc_in_o : out std_logic;
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sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
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sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
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sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
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sel_sp_as_o : OUT std_logic;
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sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
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sel_sp_in_o : OUT std_logic;
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sel_reg_o : out std_logic_vector ( 1 downto 0 );
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sync_o : OUT std_logic;
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sel_sp_as_o : out std_logic;
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wr_n_o : OUT std_logic;
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sel_sp_in_o : out std_logic;
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wr_o : OUT std_logic
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sync_o : out std_logic;
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wr_n_o : out std_logic;
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wr_o : out std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FSM_Execution_Unit ;
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end fsm_execution_unit ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- (email: opencores@vivare-services.com)
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--
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--
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-- Versions:
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- Revision 1.11 2018/09/11 11:50:00 jens
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-- - RESET generates SYNC now, 1 dead cycle delayed
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- - ADC / SBC flags and A like R6502 now
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-- - Bug Fix ADC and SBC in decimal mode (all op codes -
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-- "Overflow" flag was computed wrong)
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-- - Interrupt priority order is now: BRK - NMI - IRQ
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-- - Performance improvements on-going (Mealy -> Moore)
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-- - Bug Fixes All Branch Instructions
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-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
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-- 3 cycles now if branch forward occur and the branch
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-- instruction lies on a xxFEh location.
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-- - Bug Fix Hardware Interrupts NMI & IRQ - "SYNC" now
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--
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--
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-- Revision 1.11 BETA 2013/07/24 15:46:00 jens
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- - Changing the title block and internal revision history
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-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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--
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-- Revision 1.10 2010/02/08 17:34:20 eda
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- BUGFIX for IRQn, NMIn and RTI
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-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
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-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
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-- vector address is not loaded yet.
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--
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--
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-- Revision 1.9 2010/02/08 17:32:19 eda
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-- CVS Revisins History
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-- BUGFIX for IRQn, NMIn and RTI
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-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
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-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
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-- vector address is not loaded yet.
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--
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--
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-- Revision 1.8 2009/01/04 20:23:42 eda
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-- $Log: fsm.sm,v $
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-- *** EMERGENCY BUGFIX ***
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-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
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-- <<-- more -->>
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-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
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-- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from
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-- Title: FSM Execution Unit for all op codes
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-- $02FF and $0200, instead of $02FF and $0300)
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--
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-- Path: R6502_TC/FSM_Execution_Unit/fsm
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-- Revision 1.7 2009/01/04 16:54:59 eda
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-- - Removed unused bits in ALU (zw_ALUx)
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-- Edited: by eda on 20 Feb 2010
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--
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-- Revision 1.6 2009/01/04 10:27:49 eda
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-- Changes for cosmetic issues only
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--
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-- Revision 1.5 2009/01/04 10:25:04 eda
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-- Changes for cosmetic issues only
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--
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-- Revision 1.4 2009/01/03 16:53:01 eda
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-- - Unused nets and blocks deleted
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-- - Re-arragend symbols in block FSM_Execution_Unit
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-- - Renamed blocks
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-- - Input SO implemented
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--
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--
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-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
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-- Revision 1.3 2009/01/03 16:42:02 eda
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-- - Unused nets and blocks deleted
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-- - Re-arragend symbols in block FSM_Execution_Unit
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-- - Renamed blocks
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-- - Input SO implemented
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--
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-- Revision 1.2 2008/12/31 19:31:24 eda
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-- Production Release
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--
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--
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--
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-- VHDL Architecture r6502_tc.fsm_execution_unit.fsm
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 15:57:21 20.02.2010
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-- at - 22:31:13 15.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE fsm OF FSM_Execution_Unit IS
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architecture fsm of fsm_execution_unit is
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-- Architecture Declarations
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-- Architecture Declarations
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SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
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signal reg_F : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL reg_sel_pc_in : std_logic;
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signal reg_sel_pc_in : std_logic;
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SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
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signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
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signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
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signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
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signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL reg_sel_sp_as : std_logic;
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signal reg_sel_sp_as : std_logic;
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SIGNAL reg_sel_sp_in : std_logic;
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signal reg_sel_sp_in : std_logic;
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SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
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signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
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signal sig_PC : std_logic_vector(15 DOWNTO 0);
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SIGNAL sig_RD : std_logic;
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signal sig_RD : std_logic;
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SIGNAL sig_RWn : std_logic;
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signal sig_RWn : std_logic;
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SIGNAL sig_SYNC : std_logic;
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signal sig_SYNC : std_logic;
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SIGNAL sig_WR : std_logic;
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signal sig_WR : std_logic;
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SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
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signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
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signal zw_alu : std_logic_vector(9 DOWNTO 0);
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SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
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signal zw_alu1 : std_logic_vector(9 DOWNTO 0);
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SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
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signal zw_alu2 : std_logic_vector(9 DOWNTO 0);
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SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
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signal zw_alu3 : std_logic_vector(9 DOWNTO 0);
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SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
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signal zw_alu4 : std_logic_vector(9 DOWNTO 0);
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SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
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signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
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signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
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signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
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signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
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signal zw_bit : std_logic;
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SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
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signal zw_irq : std_logic;
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SIGNAL zw_so : std_logic;
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signal zw_ninebits4 : std_logic_vector(8 DOWNTO 0);
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signal zw_nmi : std_logic;
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signal zw_so : std_logic;
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SUBTYPE STATE_TYPE IS
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subtype state_type is
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std_logic_vector(7 DOWNTO 0);
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std_logic_vector(7 downto 0);
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-- Hard encoding
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-- Hard encoding
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CONSTANT FETCH : STATE_TYPE := "00000000";
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constant FETCH : state_type := "00000000";
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CONSTANT s1 : STATE_TYPE := "00000001";
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constant s0001 : state_type := "00000001";
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CONSTANT s2 : STATE_TYPE := "00000011";
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constant s0101 : state_type := "00000011";
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CONSTANT s5 : STATE_TYPE := "00000010";
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constant s0201 : state_type := "00000010";
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CONSTANT s3 : STATE_TYPE := "00000110";
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constant s0301 : state_type := "00000110";
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CONSTANT s4 : STATE_TYPE := "00000111";
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constant s0401 : state_type := "00000111";
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CONSTANT s12 : STATE_TYPE := "00000101";
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constant s1001 : state_type := "00000101";
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CONSTANT s16 : STATE_TYPE := "00000100";
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constant s1101 : state_type := "00000100";
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CONSTANT s17 : STATE_TYPE := "00001100";
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constant s1201 : state_type := "00001100";
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CONSTANT s24 : STATE_TYPE := "00001101";
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constant s1301 : state_type := "00001101";
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CONSTANT s25 : STATE_TYPE := "00001111";
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constant s1501 : state_type := "00001111";
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CONSTANT s271 : STATE_TYPE := "00001110";
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constant s1601 : state_type := "00001110";
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CONSTANT s273 : STATE_TYPE := "00001010";
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constant s1602 : state_type := "00001010";
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CONSTANT s304 : STATE_TYPE := "00001011";
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constant s1603 : state_type := "00001011";
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CONSTANT s307 : STATE_TYPE := "00001001";
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constant s1604 : state_type := "00001001";
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CONSTANT s177 : STATE_TYPE := "00001000";
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constant s2601 : state_type := "00001000";
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CONSTANT s180 : STATE_TYPE := "00011000";
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constant s2605 : state_type := "00011000";
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CONSTANT s181 : STATE_TYPE := "00011001";
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constant s2604 : state_type := "00011001";
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CONSTANT s182 : STATE_TYPE := "00011011";
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constant s2603 : state_type := "00011011";
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CONSTANT s183 : STATE_TYPE := "00011010";
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constant s2602 : state_type := "00011010";
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CONSTANT s184 : STATE_TYPE := "00011110";
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constant s2606 : state_type := "00011110";
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CONSTANT s185 : STATE_TYPE := "00011111";
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constant s2607 : state_type := "00011111";
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CONSTANT s186 : STATE_TYPE := "00011101";
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constant s2608 : state_type := "00011101";
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CONSTANT s187 : STATE_TYPE := "00011100";
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constant s2609 : state_type := "00011100";
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CONSTANT s188 : STATE_TYPE := "00010100";
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constant s2610 : state_type := "00010100";
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CONSTANT s189 : STATE_TYPE := "00010101";
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constant s2611 : state_type := "00010101";
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CONSTANT s190 : STATE_TYPE := "00010111";
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constant s1901 : state_type := "00010111";
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CONSTANT s191 : STATE_TYPE := "00010110";
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constant s1902 : state_type := "00010110";
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CONSTANT s192 : STATE_TYPE := "00010010";
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constant s2001 : state_type := "00010010";
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CONSTANT s193 : STATE_TYPE := "00010011";
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constant s2002 : state_type := "00010011";
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CONSTANT s377 : STATE_TYPE := "00010001";
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constant s2101 : state_type := "00010001";
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CONSTANT s381 : STATE_TYPE := "00010000";
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constant s2102 : state_type := "00010000";
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CONSTANT s378 : STATE_TYPE := "00110000";
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constant s2103 : state_type := "00110000";
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CONSTANT s382 : STATE_TYPE := "00110001";
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constant s2201 : state_type := "00110001";
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CONSTANT s379 : STATE_TYPE := "00110011";
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constant s2202 : state_type := "00110011";
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CONSTANT s383 : STATE_TYPE := "00110010";
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constant s2203 : state_type := "00110010";
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CONSTANT s384 : STATE_TYPE := "00110110";
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constant s2301 : state_type := "00110110";
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CONSTANT s380 : STATE_TYPE := "00110111";
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constant s2302 : state_type := "00110111";
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CONSTANT s385 : STATE_TYPE := "00110101";
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constant s2303 : state_type := "00110101";
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CONSTANT s386 : STATE_TYPE := "00110100";
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constant s2304 : state_type := "00110100";
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CONSTANT s387 : STATE_TYPE := "00111100";
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constant s2305 : state_type := "00111100";
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CONSTANT s388 : STATE_TYPE := "00111101";
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constant s2401 : state_type := "00111101";
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CONSTANT s389 : STATE_TYPE := "00111111";
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constant s2402 : state_type := "00111111";
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CONSTANT s391 : STATE_TYPE := "00111110";
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constant s2403 : state_type := "00111110";
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CONSTANT s392 : STATE_TYPE := "00111010";
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constant s2404 : state_type := "00111010";
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CONSTANT s390 : STATE_TYPE := "00111011";
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constant s2405 : state_type := "00111011";
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CONSTANT s393 : STATE_TYPE := "00111001";
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constant s1701 : state_type := "00111001";
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CONSTANT s394 : STATE_TYPE := "00111000";
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constant s1702 : state_type := "00111000";
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CONSTANT s395 : STATE_TYPE := "00101000";
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constant s1703 : state_type := "00101000";
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CONSTANT s396 : STATE_TYPE := "00101001";
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constant s1704 : state_type := "00101001";
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CONSTANT s397 : STATE_TYPE := "00101011";
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constant s1705 : state_type := "00101011";
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CONSTANT s398 : STATE_TYPE := "00101010";
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constant s0901 : state_type := "00101010";
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CONSTANT s399 : STATE_TYPE := "00101110";
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constant s0902 : state_type := "00101110";
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CONSTANT s400 : STATE_TYPE := "00101111";
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constant s0903 : state_type := "00101111";
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CONSTANT s401 : STATE_TYPE := "00101101";
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constant s9901 : state_type := "00101101";
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CONSTANT s526 : STATE_TYPE := "00101100";
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constant s9903 : state_type := "00101100";
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CONSTANT s527 : STATE_TYPE := "00100100";
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constant s9904 : state_type := "00100100";
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CONSTANT s528 : STATE_TYPE := "00100101";
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constant s9905 : state_type := "00100101";
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CONSTANT s529 : STATE_TYPE := "00100111";
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constant s9906 : state_type := "00100111";
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CONSTANT s530 : STATE_TYPE := "00100110";
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constant s9902 : state_type := "00100110";
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CONSTANT s531 : STATE_TYPE := "00100010";
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constant s2801 : state_type := "00100010";
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CONSTANT s544 : STATE_TYPE := "00100011";
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constant s2901 : state_type := "00100011";
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CONSTANT s545 : STATE_TYPE := "00100001";
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constant s3001 : state_type := "00100001";
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CONSTANT s546 : STATE_TYPE := "00100000";
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constant s3101 : state_type := "00100000";
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CONSTANT s547 : STATE_TYPE := "01100000";
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constant s1801 : state_type := "01100000";
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CONSTANT s549 : STATE_TYPE := "01100001";
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constant s1803 : state_type := "01100001";
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CONSTANT s550 : STATE_TYPE := "01100011";
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constant s1805 : state_type := "01100011";
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CONSTANT s404 : STATE_TYPE := "01100010";
|
constant s1806 : state_type := "01100010";
|
CONSTANT s556 : STATE_TYPE := "01100110";
|
constant s1802 : state_type := "01100110";
|
CONSTANT s557 : STATE_TYPE := "01100111";
|
constant s1804 : state_type := "01100111";
|
CONSTANT s579 : STATE_TYPE := "01100101";
|
constant s1808 : state_type := "01100101";
|
CONSTANT s201 : STATE_TYPE := "01100100";
|
constant s1807 : state_type := "01100100";
|
CONSTANT s202 : STATE_TYPE := "01101100";
|
constant s1810 : state_type := "01101100";
|
CONSTANT s210 : STATE_TYPE := "01101101";
|
constant s1809 : state_type := "01101101";
|
CONSTANT s211 : STATE_TYPE := "01101111";
|
constant s1401 : state_type := "01101111";
|
CONSTANT s215 : STATE_TYPE := "01101110";
|
constant s1403 : state_type := "01101110";
|
CONSTANT s217 : STATE_TYPE := "01101010";
|
constant s1404 : state_type := "01101010";
|
CONSTANT s218 : STATE_TYPE := "01101011";
|
constant s1402 : state_type := "01101011";
|
CONSTANT s222 : STATE_TYPE := "01101001";
|
constant s1405 : state_type := "01101001";
|
CONSTANT s223 : STATE_TYPE := "01101000";
|
constant s1406 : state_type := "01101000";
|
CONSTANT s224 : STATE_TYPE := "01111000";
|
constant s1407 : state_type := "01111000";
|
CONSTANT s225 : STATE_TYPE := "01111001";
|
constant s1408 : state_type := "01111001";
|
CONSTANT s226 : STATE_TYPE := "01111011";
|
constant s0801 : state_type := "01111011";
|
CONSTANT s243 : STATE_TYPE := "01111010";
|
constant s0803 : state_type := "01111010";
|
CONSTANT s244 : STATE_TYPE := "01111110";
|
constant s0802 : state_type := "01111110";
|
CONSTANT s247 : STATE_TYPE := "01111111";
|
constant s0601 : state_type := "01111111";
|
CONSTANT s344 : STATE_TYPE := "01111101";
|
constant s0603 : state_type := "01111101";
|
CONSTANT s343 : STATE_TYPE := "01111100";
|
constant s0604 : state_type := "01111100";
|
CONSTANT s250 : STATE_TYPE := "01110100";
|
constant s0602 : state_type := "01110100";
|
CONSTANT s251 : STATE_TYPE := "01110101";
|
constant s0605 : state_type := "01110101";
|
CONSTANT s351 : STATE_TYPE := "01110111";
|
constant s0606 : state_type := "01110111";
|
CONSTANT s361 : STATE_TYPE := "01110110";
|
constant s0607 : state_type := "01110110";
|
CONSTANT s360 : STATE_TYPE := "01110010";
|
constant s0608 : state_type := "01110010";
|
CONSTANT s403 : STATE_TYPE := "01110011";
|
constant s0501 : state_type := "01110011";
|
CONSTANT s406 : STATE_TYPE := "01110001";
|
constant s0503 : state_type := "01110001";
|
CONSTANT s407 : STATE_TYPE := "01110000";
|
constant s0505 : state_type := "01110000";
|
CONSTANT s409 : STATE_TYPE := "01010000";
|
constant s0506 : state_type := "01010000";
|
CONSTANT s412 : STATE_TYPE := "01010001";
|
constant s0502 : state_type := "01010001";
|
CONSTANT s413 : STATE_TYPE := "01010011";
|
constant s0504 : state_type := "01010011";
|
CONSTANT s416 : STATE_TYPE := "01010010";
|
constant s0507 : state_type := "01010010";
|
CONSTANT s418 : STATE_TYPE := "01010110";
|
constant s0509 : state_type := "01010110";
|
CONSTANT s510 : STATE_TYPE := "01010111";
|
constant s0510 : state_type := "01010111";
|
CONSTANT s553 : STATE_TYPE := "01010101";
|
constant s0508 : state_type := "01010101";
|
CONSTANT s555 : STATE_TYPE := "01010100";
|
constant s0701 : state_type := "01010100";
|
CONSTANT s558 : STATE_TYPE := "01011100";
|
constant s0702 : state_type := "01011100";
|
CONSTANT s560 : STATE_TYPE := "01011101";
|
constant s0703 : state_type := "01011101";
|
CONSTANT s561 : STATE_TYPE := "01011111";
|
constant s2501 : state_type := "01011111";
|
CONSTANT s563 : STATE_TYPE := "01011110";
|
constant s2503 : state_type := "01011110";
|
CONSTANT s564 : STATE_TYPE := "01011010";
|
constant s2505 : state_type := "01011010";
|
CONSTANT s565 : STATE_TYPE := "01011011";
|
constant s2506 : state_type := "01011011";
|
CONSTANT s566 : STATE_TYPE := "01011001";
|
constant s2502 : state_type := "01011001";
|
CONSTANT s266 : STATE_TYPE := "01011000";
|
constant s2504 : state_type := "01011000";
|
CONSTANT s301 : STATE_TYPE := "01001000";
|
constant s2507 : state_type := "01001000";
|
CONSTANT s302 : STATE_TYPE := "01001001";
|
constant s2508 : state_type := "01001001";
|
CONSTANT RES : STATE_TYPE := "01001011";
|
constant s2509 : state_type := "01001011";
|
CONSTANT s511 : STATE_TYPE := "01001010";
|
constant s2510 : state_type := "01001010";
|
CONSTANT s559 : STATE_TYPE := "01001110";
|
constant s2701 : state_type := "01001110";
|
CONSTANT s562 : STATE_TYPE := "01001111";
|
constant s2702 : state_type := "01001111";
|
CONSTANT s567 : STATE_TYPE := "01001101";
|
constant s2703 : state_type := "01001101";
|
CONSTANT s568 : STATE_TYPE := "01001100";
|
constant s2704 : state_type := "01001100";
|
CONSTANT s569 : STATE_TYPE := "01000100";
|
constant s2707 : state_type := "01000100";
|
CONSTANT s570 : STATE_TYPE := "01000101";
|
constant s2706 : state_type := "01000101";
|
CONSTANT s571 : STATE_TYPE := "01000111";
|
constant s2705 : state_type := "01000111";
|
CONSTANT s572 : STATE_TYPE := "01000110";
|
constant s0905 : state_type := "01000110";
|
CONSTANT s573 : STATE_TYPE := "01000010";
|
constant s0907 : state_type := "01000010";
|
CONSTANT s574 : STATE_TYPE := "01000011";
|
constant s0906 : state_type := "01000011";
|
CONSTANT s548 : STATE_TYPE := "01000001";
|
constant s0904 : state_type := "01000001";
|
CONSTANT s551 : STATE_TYPE := "01000000";
|
constant RES : state_type := "01000000";
|
CONSTANT s552 : STATE_TYPE := "11000000";
|
constant RES7 : state_type := "11000000";
|
CONSTANT s575 : STATE_TYPE := "11000001";
|
|
CONSTANT s576 : STATE_TYPE := "11000011";
|
|
CONSTANT s577 : STATE_TYPE := "11000010";
|
|
CONSTANT s578 : STATE_TYPE := "11000110";
|
|
|
|
-- Declare current and next state signals
|
-- Declare current and next state signals
|
SIGNAL current_state : STATE_TYPE;
|
signal current_state : state_type;
|
SIGNAL next_state : STATE_TYPE;
|
signal next_state : state_type;
|
|
|
-- Declare any pre-registered internal signals
|
-- Declare any pre-registered internal signals
|
SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
|
signal d_o_cld : std_logic_vector ( 7 downto 0 );
|
SIGNAL rd_o_cld : std_logic ;
|
signal rd_o_cld : std_logic ;
|
SIGNAL sync_o_cld : std_logic ;
|
signal sync_o_cld : std_logic ;
|
SIGNAL wr_n_o_cld : std_logic ;
|
signal wr_n_o_cld : std_logic ;
|
SIGNAL wr_o_cld : std_logic ;
|
signal wr_o_cld : std_logic ;
|
|
|
BEGIN
|
begin
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
clocked_proc : PROCESS (
|
clocked_proc : process (
|
clk_clk_i,
|
clk_clk_i,
|
rst_rst_n_i
|
rst_rst_n_i
|
)
|
)
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
BEGIN
|
begin
|
IF (rst_rst_n_i = '0') THEN
|
if (rst_rst_n_i = '0') then
|
current_state <= RES;
|
current_state <= RES;
|
-- Default Reset Values
|
-- Default Reset Values
|
d_o_cld <= X"00";
|
d_o_cld <= X"00";
|
rd_o_cld <= '0';
|
rd_o_cld <= '0';
|
sync_o_cld <= '0';
|
sync_o_cld <= '0';
|
wr_n_o_cld <= '1';
|
wr_n_o_cld <= '1';
|
wr_o_cld <= '0';
|
wr_o_cld <= '0';
|
reg_F <= "00000100";
|
reg_F <= "00110100";
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_rb_in <= "00";
|
reg_sel_rb_in <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
| Line 319... |
Line 355... |
zw_REG_OP <= X"00";
|
zw_REG_OP <= X"00";
|
zw_b1 <= X"00";
|
zw_b1 <= X"00";
|
zw_b2 <= X"00";
|
zw_b2 <= X"00";
|
zw_b3 <= X"00";
|
zw_b3 <= X"00";
|
zw_b4 <= X"00";
|
zw_b4 <= X"00";
|
|
zw_bit <= '0';
|
|
zw_irq <= '0';
|
|
zw_nmi <= '0';
|
zw_so <= '0';
|
zw_so <= '0';
|
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
|
elsif (clk_clk_i'event and clk_clk_i = '1') then
|
current_state <= next_state;
|
current_state <= next_state;
|
-- Default Assignment To Internals
|
-- Default Assignment To Internals
|
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
|
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
|
reg_sel_pc_in <= reg_sel_pc_in;
|
reg_sel_pc_in <= reg_sel_pc_in;
|
reg_sel_pc_val <= reg_sel_pc_val;
|
reg_sel_pc_val <= reg_sel_pc_val;
|
| Line 337... |
Line 376... |
zw_REG_OP <= zw_REG_OP;
|
zw_REG_OP <= zw_REG_OP;
|
zw_b1 <= zw_b1;
|
zw_b1 <= zw_b1;
|
zw_b2 <= zw_b2;
|
zw_b2 <= zw_b2;
|
zw_b3 <= zw_b3;
|
zw_b3 <= zw_b3;
|
zw_b4 <= zw_b4;
|
zw_b4 <= zw_b4;
|
|
zw_bit <= zw_bit;
|
|
zw_irq <= zw_irq;
|
|
zw_nmi <= zw_nmi;
|
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
|
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
|
d_o_cld <= sig_D_OUT;
|
d_o_cld <= sig_D_OUT;
|
rd_o_cld <= sig_RD;
|
rd_o_cld <= sig_RD;
|
sync_o_cld <= sig_SYNC;
|
sync_o_cld <= sig_SYNC;
|
wr_n_o_cld <= sig_RWn;
|
wr_n_o_cld <= sig_RWn;
|
wr_o_cld <= sig_WR;
|
wr_o_cld <= sig_WR;
|
|
|
-- Combined Actions
|
-- Combined Actions
|
CASE current_state IS
|
case current_state is
|
WHEN FETCH =>
|
when FETCH =>
|
zw_REG_OP <= d_i;
|
zw_REG_OP <= d_i;
|
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
|
if ((d_i = X"00") and (rdy_i = '1')) then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((irq_n_i = '0' and
|
elsif ((nmi_i = '1') and (rdy_i = '1')) then
|
reg_F(2) = '0') AND (rdy_i = '1')) THEN
|
reg_sel_pc_in <= '0';
|
sig_PC <= adr_sp_i;
|
reg_sel_pc_val <= "00";
|
ELSIF ((d_i = X"69" or
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
zw_nmi <= '0';
|
|
elsif ((irq_n_i = '0' and
|
|
reg_F(2) = '0') and (rdy_i = '1')) then
|
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
zw_irq <= '0';
|
|
elsif ((d_i = X"69" or
|
d_i = X"65" or
|
d_i = X"65" or
|
d_i = X"75" or
|
d_i = X"75" or
|
d_i = X"6D" or
|
d_i = X"6D" or
|
d_i = X"7D" or
|
d_i = X"7D" or
|
d_i = X"79" or
|
d_i = X"79" or
|
d_i = X"61" or
|
d_i = X"61" or
|
d_i = X"71") AND (rdy_i = '1')) THEN
|
d_i = X"71") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
zw_b1(0) <= reg_F(7);
|
elsif ((d_i = X"06" or
|
ELSIF ((d_i = X"06" or
|
|
d_i = X"16" or
|
d_i = X"16" or
|
d_i = X"0E" or
|
d_i = X"0E" or
|
d_i = X"1E") AND (rdy_i = '1')) THEN
|
d_i = X"1E") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"90" or
|
elsif ((d_i = X"90" or
|
d_i = X"B0" or
|
d_i = X"B0" or
|
d_i = X"F0" or
|
d_i = X"F0" or
|
d_i = X"30" or
|
d_i = X"30" or
|
d_i = X"D0" or
|
d_i = X"D0" or
|
d_i = X"10" or
|
d_i = X"10" or
|
d_i = X"50" or
|
d_i = X"50" or
|
d_i = X"70") AND (rdy_i = '1')) THEN
|
d_i = X"70") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
|
zw_b3 <= adr_nxt_pc_i (15 downto 8);
|
|
ELSIF ((d_i = X"24" or
|
|
d_i = X"2C") AND (rdy_i = '1')) THEN
|
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"24" or
|
|
d_i = X"2C") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"18") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"D8") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"58") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
|
reg_F(2) <= '0';
|
ELSIF ((d_i = X"E0" or
|
elsif ((d_i = X"B8") and (rdy_i = '1')) then
|
|
elsif ((d_i = X"E0" or
|
d_i = X"E4" or
|
d_i = X"E4" or
|
d_i = X"EC") AND (rdy_i = '1')) THEN
|
d_i = X"EC") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"C0" or
|
elsif ((d_i = X"C0" or
|
d_i = X"C4" or
|
d_i = X"C4" or
|
d_i = X"CC") AND (rdy_i = '1')) THEN
|
d_i = X"CC") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "10";
|
reg_sel_rb_out <= "10";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"C6" or
|
elsif ((d_i = X"C6" or
|
d_i = X"D6" or
|
d_i = X"D6" or
|
d_i = X"CE" or
|
d_i = X"CE" or
|
d_i = X"DE") AND (rdy_i = '1')) THEN
|
d_i = X"DE") and (rdy_i = '1')) then
|
zw_b4 <= X"FF";
|
zw_b4 <= X"FF";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"CA") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
zw_b4 <= X"FF";
|
zw_b4 <= X"FF";
|
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"88") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "10";
|
reg_sel_rb_out <= "10";
|
reg_sel_reg <= "10";
|
reg_sel_reg <= "10";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
zw_b4 <= X"FF";
|
zw_b4 <= X"FF";
|
ELSIF ((d_i = X"49" or
|
elsif ((d_i = X"49" or
|
d_i = X"45" or
|
d_i = X"45" or
|
d_i = X"55" or
|
d_i = X"55" or
|
d_i = X"4D" or
|
d_i = X"4D" or
|
d_i = X"5D" or
|
d_i = X"5D" or
|
d_i = X"59" or
|
d_i = X"59" or
|
| Line 446... |
Line 495... |
d_i = X"D5" or
|
d_i = X"D5" or
|
d_i = X"CD" or
|
d_i = X"CD" or
|
d_i = X"DD" or
|
d_i = X"DD" or
|
d_i = X"D9" or
|
d_i = X"D9" or
|
d_i = X"C1" or
|
d_i = X"C1" or
|
d_i = X"D1") AND (rdy_i = '1')) THEN
|
d_i = X"D1") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"E6" or
|
elsif ((d_i = X"E6" or
|
d_i = X"F6" or
|
d_i = X"F6" or
|
d_i = X"EE" or
|
d_i = X"EE" or
|
d_i = X"FE") AND (rdy_i = '1')) THEN
|
d_i = X"FE") and (rdy_i = '1')) then
|
zw_b4 <= X"01";
|
zw_b4 <= X"01";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"E8") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
zw_b4 <= X"01";
|
zw_b4 <= X"01";
|
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"C8") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "10";
|
reg_sel_rb_out <= "10";
|
reg_sel_reg <= "10";
|
reg_sel_reg <= "10";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
zw_b4 <= X"01";
|
zw_b4 <= X"01";
|
ELSIF ((d_i = X"4C" or
|
elsif ((d_i = X"4C" or
|
d_i = X"6C") AND (rdy_i = '1')) THEN
|
d_i = X"6C") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"20") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"A9" or
|
elsif ((d_i = X"A9" or
|
d_i = X"A5" or
|
d_i = X"A5" or
|
d_i = X"B5" or
|
d_i = X"B5" or
|
d_i = X"AD" or
|
d_i = X"AD" or
|
d_i = X"BD" or
|
d_i = X"BD" or
|
d_i = X"B9" or
|
d_i = X"B9" or
|
d_i = X"A1" or
|
d_i = X"A1" or
|
d_i = X"B1") AND (rdy_i = '1')) THEN
|
d_i = X"B1") and (rdy_i = '1')) then
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"A2" or
|
elsif ((d_i = X"A2" or
|
d_i = X"A6" or
|
d_i = X"A6" or
|
d_i = X"B6" or
|
d_i = X"B6" or
|
d_i = X"AE" or
|
d_i = X"AE" or
|
d_i = X"BE") AND (rdy_i = '1')) THEN
|
d_i = X"BE") and (rdy_i = '1')) then
|
reg_sel_reg <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"A0" or
|
elsif ((d_i = X"A0" or
|
d_i = X"A4" or
|
d_i = X"A4" or
|
d_i = X"B4" or
|
d_i = X"B4" or
|
d_i = X"AC" or
|
d_i = X"AC" or
|
d_i = X"BC") AND (rdy_i = '1')) THEN
|
d_i = X"BC") and (rdy_i = '1')) then
|
reg_sel_reg <= "10";
|
reg_sel_reg <= "10";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"46" or
|
elsif ((d_i = X"46" or
|
d_i = X"56" or
|
d_i = X"56" or
|
d_i = X"4E" or
|
d_i = X"4E" or
|
d_i = X"5E") AND (rdy_i = '1')) THEN
|
d_i = X"5E") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"EA") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"48") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"08") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"68") and (rdy_i = '1')) then
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
|
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"28") and (rdy_i = '1')) then
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"26" or
|
elsif ((d_i = X"26" or
|
d_i = X"36" or
|
d_i = X"36" or
|
d_i = X"2E" or
|
d_i = X"2E" or
|
d_i = X"3E") AND (rdy_i = '1')) THEN
|
d_i = X"3E") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"66" or
|
elsif ((d_i = X"66" or
|
d_i = X"76" or
|
d_i = X"76" or
|
d_i = X"6E" or
|
d_i = X"6E" or
|
d_i = X"7E") AND (rdy_i = '1')) THEN
|
d_i = X"7E") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"40") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"60") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"E9" or
|
elsif ((d_i = X"E9" or
|
d_i = X"E5" or
|
d_i = X"E5" or
|
d_i = X"F5" or
|
d_i = X"F5" or
|
d_i = X"ED" or
|
d_i = X"ED" or
|
d_i = X"FD" or
|
d_i = X"FD" or
|
d_i = X"F9" or
|
d_i = X"F9" or
|
d_i = X"E1" or
|
d_i = X"E1" or
|
d_i = X"F1") AND (rdy_i = '1')) THEN
|
d_i = X"F1") and (rdy_i = '1')) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
zw_b1(0) <= reg_F(7);
|
elsif ((d_i = X"38") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"F8") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"78") and (rdy_i = '1')) then
|
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
|
reg_F(2) <= '1';
|
ELSIF ((d_i = X"85" or
|
elsif ((d_i = X"85" or
|
d_i = X"95" or
|
d_i = X"95" or
|
d_i = X"8D" or
|
d_i = X"8D" or
|
d_i = X"9D" or
|
d_i = X"9D" or
|
d_i = X"99" or
|
d_i = X"99" or
|
d_i = X"81" or
|
d_i = X"81" or
|
d_i = X"91") AND (rdy_i = '1')) THEN
|
d_i = X"91") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"86" or
|
elsif ((d_i = X"86" or
|
d_i = X"96" or
|
d_i = X"96" or
|
d_i = X"8E") AND (rdy_i = '1')) THEN
|
d_i = X"8E") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"84" or
|
elsif ((d_i = X"84" or
|
d_i = X"94" or
|
d_i = X"94" or
|
d_i = X"8C") AND (rdy_i = '1')) THEN
|
d_i = X"8C") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "10";
|
reg_sel_rb_out <= "10";
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"AA") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_rb_in <= "00";
|
reg_sel_rb_in <= "00";
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"0A") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"4A") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"2A") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"6A") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"A8") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "00";
|
reg_sel_rb_out <= "00";
|
reg_sel_reg <= "10";
|
reg_sel_reg <= "10";
|
reg_sel_rb_in <= "00";
|
reg_sel_rb_in <= "00";
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"98") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "10";
|
reg_sel_rb_out <= "10";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "01";
|
reg_sel_rb_in <= "01";
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"BA") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_reg <= "01";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"8A") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
reg_sel_reg <= "00";
|
reg_sel_reg <= "00";
|
reg_sel_rb_in <= "10";
|
reg_sel_rb_in <= "10";
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"9A") and (rdy_i = '1')) then
|
reg_sel_rb_out <= "01";
|
reg_sel_rb_out <= "01";
|
reg_sel_reg <= "11";
|
reg_sel_reg <= "11";
|
reg_sel_rb_in <= "11";
|
reg_sel_rb_in <= "11";
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_in <= '1';
|
reg_sel_sp_as <= '0';
|
reg_sel_sp_as <= '0';
|
END IF;
|
end if;
|
WHEN s1 =>
|
when s0001 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s2 =>
|
when s0101 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= '1';
|
reg_F(0) <= '1';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s5 =>
|
when s0201 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(3) <= '1';
|
reg_F(3) <= '1';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s3 =>
|
when s0301 =>
|
sig_PC <= adr_pc_i;
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(2) <= '1';
|
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s4 =>
|
when s0401 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
zw_REG_OP = X"9A") THEN
|
zw_REG_OP = X"9A") then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"BA") THEN
|
zw_REG_OP = X"BA") then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s12 =>
|
when s1001 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= '0';
|
reg_F(0) <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s16 =>
|
when s1101 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(3) <= '0';
|
reg_F(3) <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s17 =>
|
when s1201 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(2) <= '0';
|
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s24 =>
|
when s1301 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(6) <= '0';
|
reg_F(6) <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s25 =>
|
when s1501 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s271 =>
|
when s1601 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
zw_REG_OP = X"4C") THEN
|
zw_REG_OP = X"4C") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
reg_sel_pc_val <= "11";
|
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"6C") THEN
|
zw_REG_OP = X"6C") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s273 =>
|
when s1602 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
|
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
zw_b2 <= d_i;
|
zw_b2 <= d_i;
|
END IF;
|
end if;
|
WHEN s304 =>
|
when s1603 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
reg_sel_pc_val <= "11";
|
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s307 =>
|
when s1604 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s177 =>
|
when s2601 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"85" OR
|
(zw_REG_OP = X"85" OR
|
zw_REG_OP = X"86" OR
|
zw_REG_OP = X"86" OR
|
zw_REG_OP = X"84")) THEN
|
zw_REG_OP = X"84")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"95" OR
|
(zw_REG_OP = X"95" OR
|
zw_REG_OP = X"94")) THEN
|
zw_REG_OP = X"94")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"8D" OR
|
(zw_REG_OP = X"8D" OR
|
zw_REG_OP = X"8E" OR
|
zw_REG_OP = X"8E" OR
|
zw_REG_OP = X"8C")) THEN
|
zw_REG_OP = X"8C")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"9D") THEN
|
zw_REG_OP = X"9D") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"99") THEN
|
zw_REG_OP = X"99") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"91") THEN
|
zw_REG_OP = X"91") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"81") THEN
|
zw_REG_OP = X"81") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"96") THEN
|
zw_REG_OP = X"96") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s180 =>
|
when s2605 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
|
zw_b3 <= d_alu_i;
|
|
END IF;
|
|
WHEN s181 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
END IF;
|
end if;
|
WHEN s182 =>
|
when s2604 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s183 =>
|
when s2603 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
END IF;
|
end if;
|
WHEN s184 =>
|
when s2602 =>
|
sig_PC <= adr_pc_i;
|
if (rdy_i = '1') then
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
WHEN s185 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s186 =>
|
when s2606 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s187 =>
|
when s2607 =>
|
sig_PC <= adr_pc_i;
|
if (rdy_i = '1') then
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
WHEN s188 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= X"00" & d_alu_i;
|
sig_PC <= X"00" & d_alu_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s189 =>
|
when s2608 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s190 =>
|
when s2609 =>
|
sig_PC <= adr_pc_i;
|
if (rdy_i = '1') then
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
WHEN s191 =>
|
|
sig_PC <= zw_b3 & zw_b1;
|
sig_PC <= zw_b3 & zw_b1;
|
WHEN s192 =>
|
end if;
|
|
when s2610 =>
|
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
WHEN s193 =>
|
end if;
|
|
when s2611 =>
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
WHEN s377 =>
|
when s1901 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s381 =>
|
when s1902 =>
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
WHEN s378 =>
|
when s2001 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s382 =>
|
when s2002 =>
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
WHEN s383 =>
|
when s2102 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s384 =>
|
when s2103 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s385 =>
|
when s2202 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s386 =>
|
when s2203 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F <= d_i;
|
reg_F(7 downto 6) <= d_i(7 downto 6);
|
|
reg_F(3 downto 0) <= d_i(3 downto 0);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s387 =>
|
when s2301 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s388 =>
|
when s2302 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s389 =>
|
when s2303 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
reg_F <= d_i;
|
reg_F <= d_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
reg_sel_pc_val <= "11";
|
end if;
|
END IF;
|
when s2304 =>
|
WHEN s391 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s392 =>
|
when s2305 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s390 =>
|
when s2401 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s393 =>
|
when s2402 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s394 =>
|
when s2403 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
END IF;
|
end if;
|
WHEN s395 =>
|
when s2404 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
END IF;
|
end if;
|
WHEN s396 =>
|
when s2405 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s397 =>
|
when s1701 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s399 =>
|
when s1703 =>
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
WHEN s400 =>
|
when s1704 =>
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
reg_sel_pc_val <= "11";
|
when s1705 =>
|
WHEN s401 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= d_i & zw_b1 (7 downto 0);
|
sig_PC <= d_i & zw_b1 (7 downto 0);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s526 =>
|
when s0901 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s527 =>
|
when s0902 =>
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
WHEN s528 =>
|
when s0903 =>
|
sig_PC <= adr_sp_i;
|
|
WHEN s529 =>
|
|
sig_PC <= X"FFFE";
|
|
WHEN s530 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= d_i & zw_b1;
|
|
reg_F(2) <= '1';
|
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
END IF;
|
|
WHEN s531 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= X"FFFF";
|
|
reg_sel_pc_in <= '1';
|
|
|
|
reg_sel_pc_val <= "11";
|
|
zw_b1 <= d_i;
|
|
END IF;
|
|
WHEN s544 =>
|
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
WHEN s545 =>
|
when s9901 =>
|
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
|
end if;
|
|
when s9903 =>
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
|
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
WHEN s546 =>
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_sp_i;
|
WHEN s547 =>
|
end if;
|
IF (rdy_i = '1') THEN
|
when s9904 =>
|
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
end if;
|
|
when s9905 =>
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
|
if (rdy_i = '1') then
|
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
reg_sel_pc_val <= "11";
|
end if;
|
END IF;
|
when s9906 =>
|
WHEN s549 =>
|
reg_F(2) <= '1';
|
IF (rdy_i = '1') THEN
|
reg_F(5) <= '1';
|
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s550 =>
|
when s9902 =>
|
sig_PC <= adr_sp_i;
|
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
|
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
WHEN s404 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
sig_PC <= adr_sp_i;
|
|
end if;
|
|
when s2801 =>
|
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= q_a_i(7);
|
reg_F(0) <= q_a_i(7);
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s556 =>
|
when s2901 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= q_a_i(0);
|
reg_F(0) <= q_a_i(0);
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s557 =>
|
when s3001 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= q_a_i(7);
|
reg_F(0) <= q_a_i(7);
|
reg_F(0) <= q_a_i(7);
|
reg_F(0) <= q_a_i(7);
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s579 =>
|
when s3101 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= q_a_i(0);
|
reg_F(0) <= q_a_i(0);
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s201 =>
|
when s1801 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
|
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
|
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
|
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
|
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
|
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
|
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
|
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF ((rdy_i = '1' and
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1' and
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1' and
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1' and
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= zw_ALU(8);
|
reg_F(0) <= zw_ALU(8);
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_ALU(0)));
|
(zw_ALU(0)));
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"B5" OR
|
(zw_REG_OP = X"B5" OR
|
zw_REG_OP = X"B4" OR
|
zw_REG_OP = X"B4" OR
|
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
|
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
|
zw_REG_OP = X"35" OR
|
zw_REG_OP = X"35" OR
|
zw_REG_OP = X"D5")) THEN
|
zw_REG_OP = X"D5")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"AD" OR
|
(zw_REG_OP = X"AD" OR
|
zw_REG_OP = X"AE" OR
|
zw_REG_OP = X"AE" OR
|
zw_REG_OP = X"AC" OR
|
zw_REG_OP = X"AC" OR
|
zw_REG_OP = X"4D" OR
|
zw_REG_OP = X"4D" OR
|
zw_REG_OP = X"0D" OR
|
zw_REG_OP = X"0D" OR
|
zw_REG_OP = X"2D" OR
|
zw_REG_OP = X"2D" OR
|
zw_REG_OP = X"CD" OR
|
zw_REG_OP = X"CD" OR
|
zw_REG_OP = X"EC" OR
|
zw_REG_OP = X"EC" OR
|
zw_REG_OP = X"CC")) THEN
|
zw_REG_OP = X"CC")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"BD" OR
|
(zw_REG_OP = X"BD" OR
|
zw_REG_OP = X"BC" OR
|
zw_REG_OP = X"BC" OR
|
zw_REG_OP = X"5D" OR
|
zw_REG_OP = X"5D" OR
|
zw_REG_OP = X"1D" OR
|
zw_REG_OP = X"1D" OR
|
zw_REG_OP = X"3D" OR
|
zw_REG_OP = X"3D" OR
|
zw_REG_OP = X"DD")) THEN
|
zw_REG_OP = X"DD")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"B9" OR
|
(zw_REG_OP = X"B9" OR
|
zw_REG_OP = X"BE" OR
|
zw_REG_OP = X"BE" OR
|
zw_REG_OP = X"59" OR
|
zw_REG_OP = X"59" OR
|
zw_REG_OP = X"19" OR
|
zw_REG_OP = X"19" OR
|
zw_REG_OP = X"39" OR
|
zw_REG_OP = X"39" OR
|
zw_REG_OP = X"D9")) THEN
|
zw_REG_OP = X"D9")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"B1" OR
|
(zw_REG_OP = X"B1" OR
|
zw_REG_OP = X"51" OR
|
zw_REG_OP = X"51" OR
|
zw_REG_OP = X"11" OR
|
zw_REG_OP = X"11" OR
|
zw_REG_OP = X"31" OR
|
zw_REG_OP = X"31" OR
|
zw_REG_OP = X"D1")) THEN
|
zw_REG_OP = X"D1")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"A1" OR
|
(zw_REG_OP = X"A1" OR
|
zw_REG_OP = X"41" OR
|
zw_REG_OP = X"41" OR
|
zw_REG_OP = X"01" OR
|
zw_REG_OP = X"01" OR
|
zw_REG_OP = X"21" OR
|
zw_REG_OP = X"21" OR
|
zw_REG_OP = X"C1")) THEN
|
zw_REG_OP = X"C1")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"B6") THEN
|
zw_REG_OP = X"B6") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s202 =>
|
when s1803 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
|
END IF;
|
|
WHEN s210 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
end if;
|
END IF;
|
when s1805 =>
|
WHEN s211 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s215 =>
|
when s1806 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
END IF;
|
end if;
|
WHEN s217 =>
|
when s1802 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s218 =>
|
when s1804 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s222 =>
|
when s1808 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & d_alu_i;
|
sig_PC <= X"00" & d_alu_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s223 =>
|
when s1807 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s224 =>
|
when s1810 =>
|
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= zw_ALU(8);
|
reg_F(0) <= zw_ALU(8);
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_ALU(0)));
|
(zw_ALU(0)));
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s225 =>
|
when s1809 =>
|
IF ((rdy_i = '1' AND
|
if ((rdy_i = '1' AND
|
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1' AND
|
elsif ((rdy_i = '1' AND
|
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1' AND
|
elsif ((rdy_i = '1' AND
|
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF ((rdy_i = '1' AND
|
elsif ((rdy_i = '1' AND
|
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= zw_ALU(8);
|
reg_F(0) <= zw_ALU(8);
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_ALU(0)));
|
(zw_ALU(0)));
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' AND
|
elsif (rdy_i = '1' AND
|
zw_b2(0) = '0') THEN
|
zw_b2(0) = '0') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= zw_b3 & zw_b1;
|
sig_PC <= zw_b3 & zw_b1;
|
END IF;
|
end if;
|
WHEN s226 =>
|
when s1401 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"C6" OR
|
(zw_REG_OP = X"C6" OR
|
zw_REG_OP = X"E6")) THEN
|
zw_REG_OP = X"E6")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"D6" OR
|
(zw_REG_OP = X"D6" OR
|
zw_REG_OP = X"F6")) THEN
|
zw_REG_OP = X"F6")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"CE" OR
|
(zw_REG_OP = X"CE" OR
|
zw_REG_OP = X"EE")) THEN
|
zw_REG_OP = X"EE")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"DE" OR
|
(zw_REG_OP = X"DE" OR
|
zw_REG_OP = X"FE")) THEN
|
zw_REG_OP = X"FE")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
END IF;
|
end if;
|
WHEN s243 =>
|
when s1403 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
END IF;
|
end if;
|
WHEN s244 =>
|
when s1404 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s247 =>
|
when s1402 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s344 =>
|
when s1405 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= zw_b3 & zw_b1;
|
sig_PC <= zw_b3 & zw_b1;
|
END IF;
|
end if;
|
WHEN s343 =>
|
when s1406 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s251 =>
|
when s1408 =>
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
WHEN s351 =>
|
when s0801 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
zw_REG_OP = X"24") THEN
|
zw_REG_OP = X"24") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"2C") THEN
|
zw_REG_OP = X"2C") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s361 =>
|
when s0803 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(7) <= d_i(7);
|
reg_F(7) <= d_i(7);
|
reg_F(6) <= d_i(6);
|
reg_F(6) <= d_i(6);
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s360 =>
|
when s0802 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
END IF;
|
end if;
|
WHEN s403 =>
|
when s0601 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"1E" or
|
(zw_REG_OP = X"1E" or
|
zw_REG_OP = X"7E" or
|
zw_REG_OP = X"7E" or
|
zw_REG_OP = X"3E" or
|
zw_REG_OP = X"3E" or
|
zw_REG_OP = X"5E")) THEN
|
zw_REG_OP = X"5E")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"06" or
|
(zw_REG_OP = X"06" or
|
zw_REG_OP = X"66" or
|
zw_REG_OP = X"66" or
|
zw_REG_OP = X"26" or
|
zw_REG_OP = X"26" or
|
zw_REG_OP = X"46")) THEN
|
zw_REG_OP = X"46")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"16" or
|
(zw_REG_OP = X"16" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"56")) THEN
|
zw_REG_OP = X"56")) then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"0E" or
|
(zw_REG_OP = X"0E" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"4E")) THEN
|
zw_REG_OP = X"4E")) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s406 =>
|
when s0603 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
END IF;
|
end if;
|
WHEN s407 =>
|
when s0604 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s409 =>
|
when s0602 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s412 =>
|
when s0605 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= zw_b3 & zw_b1;
|
sig_PC <= zw_b3 & zw_b1;
|
END IF;
|
end if;
|
WHEN s416 =>
|
when s0607 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"06" or
|
(zw_REG_OP = X"06" or
|
zw_REG_OP = X"16" or
|
zw_REG_OP = X"16" or
|
zw_REG_OP = X"0E" or
|
zw_REG_OP = X"0E" or
|
zw_REG_OP = X"1E")) THEN
|
zw_REG_OP = X"1E")) then
|
zw_b1 <= d_i(6 downto 0) & '0';
|
zw_b1 <= d_i(6 downto 0) & '0';
|
zw_b2(0) <= d_i(7);
|
zw_b2(0) <= d_i(7);
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"46" or
|
(zw_REG_OP = X"46" or
|
zw_REG_OP = X"56" or
|
zw_REG_OP = X"56" or
|
zw_REG_OP = X"4E" or
|
zw_REG_OP = X"4E" or
|
zw_REG_OP = X"5E")) THEN
|
zw_REG_OP = X"5E")) then
|
zw_b1 <= '0' & d_i(7 downto 1);
|
zw_b1 <= '0' & d_i(7 downto 1);
|
zw_b2(0) <= d_i(0);
|
zw_b2(0) <= d_i(0);
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"26" or
|
(zw_REG_OP = X"26" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"3E")) THEN
|
zw_REG_OP = X"3E")) then
|
zw_b1 <= d_i(6 downto 0) & reg_F(0);
|
zw_b1 <= d_i(6 downto 0) & reg_F(0);
|
zw_b2(0) <= d_i(7);
|
zw_b2(0) <= d_i(7);
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"66" or
|
(zw_REG_OP = X"66" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"7E")) THEN
|
zw_REG_OP = X"7E")) then
|
zw_b1 <= reg_F(0) & d_i(7 downto 1);
|
zw_b1 <= reg_F(0) & d_i(7 downto 1);
|
zw_b2(0) <= d_i(0);
|
zw_b2(0) <= d_i(0);
|
END IF;
|
end if;
|
WHEN s418 =>
|
when s0608 =>
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_F(0) <= zw_b2(0);
|
reg_F(0) <= zw_b2(0);
|
reg_F(7) <= reg_7flag_i;
|
reg_F(7) <= reg_7flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_F(1) <= reg_1flag_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
WHEN s510 =>
|
when s0501 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
zw_REG_OP = X"65") THEN
|
zw_REG_OP = X"65") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"69" and
|
zw_REG_OP = X"69" and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_alu(7);
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7)));
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
|
(zw_ALU(0)));
|
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
|
reg_F(0) <= zw_ALU(8);
|
zw_alu(0));
|
|
reg_F(0) <= zw_alu(8);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"75") THEN
|
zw_REG_OP = X"75") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"6D") THEN
|
zw_REG_OP = X"6D") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"7D") THEN
|
zw_REG_OP = X"7D") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"79") THEN
|
zw_REG_OP = X"79") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"71") THEN
|
zw_REG_OP = X"71") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"61") THEN
|
zw_REG_OP = X"61") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"69" and
|
zw_REG_OP = X"69" and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= zw_alu(9) OR
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
(zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(zw_alu(8) AND zw_alu(7)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_alu(8) AND zw_alu(6));
|
(zw_ALU(0)));
|
|
reg_F(0) <= zw_ALU4(4);
|
reg_F(1) <= (NOT(zw_alu(4) OR
|
|
zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR
|
|
zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR
|
|
(zw_alu(4) AND
|
|
zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND
|
|
NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0))));
|
|
|
|
reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
|
|
reg_F(7) <= zw_alu2(5);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s553 =>
|
when s0503 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
END IF;
|
end if;
|
WHEN s555 =>
|
when s0505 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s558 =>
|
when s0506 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
END IF;
|
end if;
|
WHEN s560 =>
|
when s0502 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s561 =>
|
when s0504 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s563 =>
|
when s0507 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & d_alu_i;
|
sig_PC <= X"00" & d_alu_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s564 =>
|
when s0509 =>
|
IF (rdy_i = '1' AND
|
if (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_alu(7);
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7)));
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
|
(zw_ALU(0)));
|
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
|
reg_F(0) <= zw_ALU(8);
|
zw_alu(0));
|
|
reg_F(0) <= zw_alu(8);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' AND
|
elsif (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= zw_alu(9) OR
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
(zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(zw_alu(8) AND zw_alu(7)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_alu(8) AND zw_alu(6));
|
(zw_ALU(0)));
|
|
reg_F(0) <= zw_ALU4(4);
|
reg_F(1) <= (NOT(zw_alu(4) OR
|
|
zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR
|
|
zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR
|
|
(zw_alu(4) AND
|
|
zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND
|
|
NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0))));
|
|
|
|
reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
|
|
reg_F(7) <= zw_alu2(5);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= zw_b3 & zw_b1;
|
sig_PC <= zw_b3 & zw_b1;
|
END IF;
|
end if;
|
WHEN s565 =>
|
when s0510 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_alu(7);
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7)));
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
|
(zw_ALU(0)));
|
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
|
reg_F(0) <= zw_ALU(8);
|
zw_alu(0));
|
|
reg_F(0) <= zw_alu(8);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= zw_alu(9) OR
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
(zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(zw_alu(8) AND zw_alu(7)) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
(zw_alu(8) AND zw_alu(6));
|
(zw_ALU(0)));
|
|
reg_F(0) <= zw_ALU4(4);
|
reg_F(1) <= (NOT(zw_alu(4) OR
|
|
zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR
|
|
zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR
|
|
(zw_alu(4) AND
|
|
zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND
|
|
NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0))));
|
|
|
|
reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
|
|
reg_F(7) <= zw_alu2(5);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s566 =>
|
when s0508 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s266 =>
|
when s0701 =>
|
IF (rdy_i = '1' and (
|
zw_b3 <= adr_nxt_pc_i (15 downto 8);
|
|
if (rdy_i = '1' and (
|
(reg_F(0) = '1' and zw_REG_OP = X"90") or
|
(reg_F(0) = '1' and zw_REG_OP = X"90") or
|
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
|
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
|
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
|
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
|
(reg_F(7) = '0' and zw_REG_OP = X"30") or
|
(reg_F(7) = '0' and zw_REG_OP = X"30") or
|
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
|
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
|
(reg_F(7) = '1' and zw_REG_OP = X"10") or
|
(reg_F(7) = '1' and zw_REG_OP = X"10") or
|
(reg_F(6) = '1' and zw_REG_OP = X"50") or
|
(reg_F(6) = '1' and zw_REG_OP = X"50") or
|
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
|
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
|
|
reg_sel_pc_val <= "10";
|
reg_sel_pc_val <= "10";
|
zw_b2 <= d_i;
|
zw_b2 <= d_i;
|
END IF;
|
end if;
|
WHEN s301 =>
|
when s0702 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
|
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
|
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
|
END IF;
|
end if;
|
WHEN s302 =>
|
when s0703 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN RES =>
|
when s2501 =>
|
reg_sel_pc_in <= '0';
|
if (rdy_i = '1' and
|
reg_sel_pc_val <= "00";
|
zw_REG_OP = X"E5") then
|
sig_PC <= adr_nxt_pc_i;
|
|
reg_sel_pc_in <= '0';
|
|
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
WHEN s511 =>
|
|
IF (rdy_i = '1' and
|
|
zw_REG_OP = X"E5") THEN
|
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"E9" and
|
zw_REG_OP = X"E9" and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_alu(7);
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7)));
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
|
(zw_ALU(0)));
|
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
|
reg_F(0) <= zw_ALU(8);
|
zw_alu(0));
|
|
reg_F(0) <= zw_alu(8);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"F5") THEN
|
zw_REG_OP = X"F5") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"ED") THEN
|
zw_REG_OP = X"ED") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"FD") THEN
|
zw_REG_OP = X"FD") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"F9") THEN
|
zw_REG_OP = X"F9") then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"F1") THEN
|
zw_REG_OP = X"F1") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"E1") THEN
|
zw_REG_OP = X"E1") then
|
sig_PC <= X"00" & d_i;
|
sig_PC <= X"00" & d_i;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"E9" and
|
zw_REG_OP = X"E9" and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
sig_PC <= adr_nxt_pc_i;
|
sig_PC <= adr_nxt_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= (zw_alu2(4));
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0));
|
(zw_ALU(0)));
|
|
reg_F(0) <= zw_ALU2(4);
|
reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7)));
|
|
reg_F(7) <= zw_alu2(6);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s559 =>
|
when s2503 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
|
END IF;
|
|
WHEN s562 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
end if;
|
END IF;
|
when s2505 =>
|
WHEN s567 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s568 =>
|
when s2506 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
zw_b1 <= d_alu_i;
|
zw_b1 <= d_alu_i;
|
zw_b2(0) <= reg_0flag_i;
|
zw_b2(0) <= reg_0flag_i;
|
END IF;
|
end if;
|
WHEN s569 =>
|
when s2502 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s570 =>
|
when s2504 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & zw_b1;
|
sig_PC <= X"00" & zw_b1;
|
END IF;
|
end if;
|
WHEN s571 =>
|
when s2507 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
zw_b3 <= d_alu_i;
|
zw_b3 <= d_alu_i;
|
END IF;
|
end if;
|
WHEN s572 =>
|
when s2508 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"00" & d_alu_i;
|
sig_PC <= X"00" & d_alu_i;
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN s573 =>
|
when s2509 =>
|
IF (rdy_i = '1' AND
|
if (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_alu(7);
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7)));
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
|
(zw_ALU(0)));
|
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
|
reg_F(0) <= zw_ALU(8);
|
zw_alu(0));
|
|
reg_F(0) <= zw_alu(8);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' AND
|
elsif (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= (zw_alu2(4));
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0));
|
(zw_ALU(0)));
|
|
reg_F(0) <= zw_ALU2(4);
|
reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7)));
|
|
reg_F(7) <= zw_alu2(6);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1') THEN
|
elsif (rdy_i = '1') then
|
sig_PC <= zw_b3 & zw_b1;
|
sig_PC <= zw_b3 & zw_b1;
|
END IF;
|
end if;
|
WHEN s574 =>
|
when s2510 =>
|
IF (rdy_i = '1' and
|
if (rdy_i = '1' and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(7) <= zw_alu(7);
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
(NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7)));
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
|
(zw_ALU(0)));
|
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
|
reg_F(0) <= zw_ALU(8);
|
zw_alu(0));
|
|
reg_F(0) <= zw_alu(8);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
ELSIF (rdy_i = '1' and
|
elsif (rdy_i = '1' and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
sig_PC <= adr_pc_i;
|
sig_PC <= adr_pc_i;
|
|
|
reg_F(7) <= zw_ALU(7);
|
reg_F(0) <= (zw_alu2(4));
|
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
|
|
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
|
reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR
|
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
|
zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0));
|
(zw_ALU(0)));
|
|
reg_F(0) <= zw_ALU2(4);
|
reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7)));
|
|
reg_F(7) <= zw_alu2(6);
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s548 =>
|
when s2701 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
END IF;
|
end if;
|
WHEN s551 =>
|
when s2702 =>
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
WHEN s552 =>
|
when s2703 =>
|
sig_PC <= adr_sp_i;
|
sig_PC <= adr_sp_i;
|
WHEN s575 =>
|
when s2704 =>
|
IF (rdy_i = '1') THEN
|
if (nmi_i = '1') then
|
sig_PC <= X"FFFF";
|
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "11";
|
|
reg_F(2) <= '1';
|
|
zw_b1 <= d_i;
|
|
END IF;
|
|
WHEN s576 =>
|
|
IF (NMI_i = '1') THEN
|
|
sig_PC <= X"FFFA";
|
sig_PC <= X"FFFA";
|
ELSE
|
else
|
sig_PC <= X"FFFE";
|
sig_PC <= X"FFFE";
|
END IF;
|
end if;
|
WHEN s577 =>
|
when s2707 =>
|
IF (rdy_i = '1') THEN
|
reg_F(2) <= '1';
|
|
if (rdy_i = '1') then
|
sig_PC <= d_i & zw_b1;
|
sig_PC <= d_i & zw_b1;
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_in <= '0';
|
reg_sel_pc_val <= "00";
|
reg_sel_pc_val <= "00";
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_in <= '0';
|
reg_sel_sp_as <= '1';
|
reg_sel_sp_as <= '1';
|
END IF;
|
end if;
|
WHEN s578 =>
|
when s2706 =>
|
IF (rdy_i = '1') THEN
|
if (rdy_i = '1') then
|
sig_PC <= X"FFFB";
|
sig_PC <= X"FFFB";
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_in <= '1';
|
reg_sel_pc_val <= "11";
|
reg_sel_pc_val <= "01";
|
|
zw_b1 <= d_i;
|
|
end if;
|
|
when s2705 =>
|
|
if (rdy_i = '1') then
|
|
sig_PC <= X"FFFF";
|
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
|
zw_b1 <= d_i;
|
|
end if;
|
|
when s0905 =>
|
|
if (rdy_i = '1') then
|
|
sig_PC <= X"FFFF";
|
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
|
zw_b1 <= d_i;
|
|
end if;
|
|
when s0907 =>
|
reg_F(2) <= '1';
|
reg_F(2) <= '1';
|
|
if (rdy_i = '1') then
|
|
sig_PC <= d_i & zw_b1;
|
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
end if;
|
|
when s0906 =>
|
|
if (rdy_i = '1') then
|
|
sig_PC <= X"FFFB";
|
|
reg_sel_pc_in <= '1';
|
|
reg_sel_pc_val <= "01";
|
zw_b1 <= d_i;
|
zw_b1 <= d_i;
|
END IF;
|
end if;
|
WHEN OTHERS =>
|
when s0904 =>
|
NULL;
|
if (nmi_i = '1') then
|
END CASE;
|
sig_PC <= X"FFFA";
|
END IF;
|
else
|
END PROCESS clocked_proc;
|
sig_PC <= X"FFFE";
|
|
end if;
|
|
when RES =>
|
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
when RES7 =>
|
|
sig_PC <= adr_nxt_pc_i;
|
|
reg_sel_pc_in <= '0';
|
|
reg_sel_pc_val <= "00";
|
|
reg_sel_sp_in <= '0';
|
|
reg_sel_sp_as <= '1';
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end if;
|
|
end process clocked_proc;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
nextstate_proc : PROCESS (
|
nextstate_proc : process (
|
adr_nxt_pc_i,
|
adr_nxt_pc_i,
|
|
adr_pc_i,
|
|
adr_sp_i,
|
current_state,
|
current_state,
|
|
d_alu_i,
|
d_i,
|
d_i,
|
|
d_regs_out_i,
|
irq_n_i,
|
irq_n_i,
|
nmi_i,
|
nmi_i,
|
|
q_a_i,
|
|
q_x_i,
|
|
q_y_i,
|
rdy_i,
|
rdy_i,
|
reg_F,
|
reg_F,
|
|
reg_sel_pc_in,
|
|
reg_sel_pc_val,
|
|
reg_sel_rb_in,
|
|
reg_sel_rb_out,
|
|
reg_sel_reg,
|
|
reg_sel_sp_as,
|
|
reg_sel_sp_in,
|
|
sig_PC,
|
zw_REG_OP,
|
zw_REG_OP,
|
|
zw_alu,
|
|
zw_alu1,
|
|
zw_alu2,
|
|
zw_alu3,
|
|
zw_b1,
|
zw_b2,
|
zw_b2,
|
zw_b3
|
zw_b3,
|
|
zw_b4
|
)
|
)
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
BEGIN
|
begin
|
CASE current_state IS
|
|
WHEN FETCH =>
|
|
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
|
|
next_state <= s548;
|
|
ELSIF ((irq_n_i = '0' and
|
|
reg_F(2) = '0') AND (rdy_i = '1')) THEN
|
|
next_state <= s548;
|
|
ELSIF ((d_i = X"69" or
|
|
d_i = X"65" or
|
|
d_i = X"75" or
|
|
d_i = X"6D" or
|
|
d_i = X"7D" or
|
|
d_i = X"79" or
|
|
d_i = X"61" or
|
|
d_i = X"71") AND (rdy_i = '1')) THEN
|
|
next_state <= s510;
|
|
ELSIF ((d_i = X"06" or
|
|
d_i = X"16" or
|
|
d_i = X"0E" or
|
|
d_i = X"1E") AND (rdy_i = '1')) THEN
|
|
next_state <= s403;
|
|
ELSIF ((d_i = X"90" or
|
|
d_i = X"B0" or
|
|
d_i = X"F0" or
|
|
d_i = X"30" or
|
|
d_i = X"D0" or
|
|
d_i = X"10" or
|
|
d_i = X"50" or
|
|
d_i = X"70") AND (rdy_i = '1')) THEN
|
|
next_state <= s266;
|
|
ELSIF ((d_i = X"24" or
|
|
d_i = X"2C") AND (rdy_i = '1')) THEN
|
|
next_state <= s351;
|
|
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
|
|
next_state <= s526;
|
|
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
|
|
next_state <= s12;
|
|
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
|
|
next_state <= s16;
|
|
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
|
|
next_state <= s17;
|
|
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
|
|
next_state <= s24;
|
|
ELSIF ((d_i = X"E0" or
|
|
d_i = X"E4" or
|
|
d_i = X"EC") AND (rdy_i = '1')) THEN
|
|
next_state <= s201;
|
|
ELSIF ((d_i = X"C0" or
|
|
d_i = X"C4" or
|
|
d_i = X"CC") AND (rdy_i = '1')) THEN
|
|
next_state <= s201;
|
|
ELSIF ((d_i = X"C6" or
|
|
d_i = X"D6" or
|
|
d_i = X"CE" or
|
|
d_i = X"DE") AND (rdy_i = '1')) THEN
|
|
next_state <= s226;
|
|
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
|
|
next_state <= s25;
|
|
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
|
|
next_state <= s25;
|
|
ELSIF ((d_i = X"49" or
|
|
d_i = X"45" or
|
|
d_i = X"55" or
|
|
d_i = X"4D" or
|
|
d_i = X"5D" or
|
|
d_i = X"59" or
|
|
d_i = X"41" or
|
|
d_i = X"51" or
|
|
d_i = X"09" or
|
|
d_i = X"05" or
|
|
d_i = X"15" or
|
|
d_i = X"0D" or
|
|
d_i = X"1D" or
|
|
d_i = X"19" or
|
|
d_i = X"01" or
|
|
d_i = X"11" or
|
|
d_i = X"29" or
|
|
d_i = X"25" or
|
|
d_i = X"35" or
|
|
d_i = X"2D" or
|
|
d_i = X"3D" or
|
|
d_i = X"39" or
|
|
d_i = X"21" or
|
|
d_i = X"31" or
|
|
d_i = X"C9" or
|
|
d_i = X"C5" or
|
|
d_i = X"D5" or
|
|
d_i = X"CD" or
|
|
d_i = X"DD" or
|
|
d_i = X"D9" or
|
|
d_i = X"C1" or
|
|
d_i = X"D1") AND (rdy_i = '1')) THEN
|
|
next_state <= s201;
|
|
ELSIF ((d_i = X"E6" or
|
|
d_i = X"F6" or
|
|
d_i = X"EE" or
|
|
d_i = X"FE") AND (rdy_i = '1')) THEN
|
|
next_state <= s226;
|
|
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
|
|
next_state <= s25;
|
|
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
|
|
next_state <= s25;
|
|
ELSIF ((d_i = X"4C" or
|
|
d_i = X"6C") AND (rdy_i = '1')) THEN
|
|
next_state <= s271;
|
|
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
|
|
next_state <= s397;
|
|
ELSIF ((d_i = X"A9" or
|
|
d_i = X"A5" or
|
|
d_i = X"B5" or
|
|
d_i = X"AD" or
|
|
d_i = X"BD" or
|
|
d_i = X"B9" or
|
|
d_i = X"A1" or
|
|
d_i = X"B1") AND (rdy_i = '1')) THEN
|
|
next_state <= s201;
|
|
ELSIF ((d_i = X"A2" or
|
|
d_i = X"A6" or
|
|
d_i = X"B6" or
|
|
d_i = X"AE" or
|
|
d_i = X"BE") AND (rdy_i = '1')) THEN
|
|
next_state <= s201;
|
|
ELSIF ((d_i = X"A0" or
|
|
d_i = X"A4" or
|
|
d_i = X"B4" or
|
|
d_i = X"AC" or
|
|
d_i = X"BC") AND (rdy_i = '1')) THEN
|
|
next_state <= s201;
|
|
ELSIF ((d_i = X"46" or
|
|
d_i = X"56" or
|
|
d_i = X"4E" or
|
|
d_i = X"5E") AND (rdy_i = '1')) THEN
|
|
next_state <= s403;
|
|
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
|
|
next_state <= s1;
|
|
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
|
|
next_state <= s377;
|
|
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
|
|
next_state <= s378;
|
|
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
|
|
next_state <= s379;
|
|
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
|
|
next_state <= s380;
|
|
ELSIF ((d_i = X"26" or
|
|
d_i = X"36" or
|
|
d_i = X"2E" or
|
|
d_i = X"3E") AND (rdy_i = '1')) THEN
|
|
next_state <= s403;
|
|
ELSIF ((d_i = X"66" or
|
|
d_i = X"76" or
|
|
d_i = X"6E" or
|
|
d_i = X"7E") AND (rdy_i = '1')) THEN
|
|
next_state <= s403;
|
|
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
|
|
next_state <= s387;
|
|
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
|
|
next_state <= s390;
|
|
ELSIF ((d_i = X"E9" or
|
|
d_i = X"E5" or
|
|
d_i = X"F5" or
|
|
d_i = X"ED" or
|
|
d_i = X"FD" or
|
|
d_i = X"F9" or
|
|
d_i = X"E1" or
|
|
d_i = X"F1") AND (rdy_i = '1')) THEN
|
|
next_state <= s511;
|
|
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
|
|
next_state <= s2;
|
|
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
|
|
next_state <= s5;
|
|
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
|
|
next_state <= s3;
|
|
ELSIF ((d_i = X"85" or
|
|
d_i = X"95" or
|
|
d_i = X"8D" or
|
|
d_i = X"9D" or
|
|
d_i = X"99" or
|
|
d_i = X"81" or
|
|
d_i = X"91") AND (rdy_i = '1')) THEN
|
|
next_state <= s177;
|
|
ELSIF ((d_i = X"86" or
|
|
d_i = X"96" or
|
|
d_i = X"8E") AND (rdy_i = '1')) THEN
|
|
next_state <= s177;
|
|
ELSIF ((d_i = X"84" or
|
|
d_i = X"94" or
|
|
d_i = X"8C") AND (rdy_i = '1')) THEN
|
|
next_state <= s177;
|
|
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
|
|
next_state <= s4;
|
|
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
|
|
next_state <= s404;
|
|
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
|
|
next_state <= s556;
|
|
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
|
|
next_state <= s557;
|
|
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
|
|
next_state <= s579;
|
|
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
|
|
next_state <= s4;
|
|
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
|
|
next_state <= s4;
|
|
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
|
|
next_state <= s4;
|
|
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
|
|
next_state <= s4;
|
|
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
|
|
next_state <= s4;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= s1;
|
|
ELSE
|
|
next_state <= FETCH;
|
|
END IF;
|
|
WHEN s1 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s1;
|
|
END IF;
|
|
WHEN s2 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s2;
|
|
END IF;
|
|
WHEN s5 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s5;
|
|
END IF;
|
|
WHEN s3 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s3;
|
|
END IF;
|
|
WHEN s4 =>
|
|
IF (rdy_i = '1' and
|
|
zw_REG_OP = X"9A") THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"BA") THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s4;
|
|
END IF;
|
|
WHEN s12 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s12;
|
|
END IF;
|
|
WHEN s16 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s16;
|
|
END IF;
|
|
WHEN s17 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s17;
|
|
END IF;
|
|
WHEN s24 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s24;
|
|
END IF;
|
|
WHEN s25 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s25;
|
|
END IF;
|
|
WHEN s271 =>
|
|
IF (rdy_i = '1' and
|
|
zw_REG_OP = X"4C") THEN
|
|
next_state <= s307;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"6C") THEN
|
|
next_state <= s273;
|
|
ELSE
|
|
next_state <= s271;
|
|
END IF;
|
|
WHEN s273 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s304;
|
|
ELSE
|
|
next_state <= s273;
|
|
END IF;
|
|
WHEN s304 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s307;
|
|
ELSE
|
|
next_state <= s304;
|
|
END IF;
|
|
WHEN s307 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s307;
|
|
END IF;
|
|
WHEN s177 =>
|
|
IF (rdy_i = '1' and
|
|
(zw_REG_OP = X"85" OR
|
|
zw_REG_OP = X"86" OR
|
|
zw_REG_OP = X"84")) THEN
|
|
next_state <= s184;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"95" OR
|
|
zw_REG_OP = X"94")) THEN
|
|
next_state <= s185;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"8D" OR
|
|
zw_REG_OP = X"8E" OR
|
|
zw_REG_OP = X"8C")) THEN
|
|
next_state <= s183;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"9D") THEN
|
|
next_state <= s182;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"99") THEN
|
|
next_state <= s180;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"91") THEN
|
|
next_state <= s181;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"81") THEN
|
|
next_state <= s186;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"96") THEN
|
|
next_state <= s185;
|
|
ELSE
|
|
next_state <= s177;
|
|
END IF;
|
|
WHEN s180 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s191;
|
|
ELSE
|
|
next_state <= s180;
|
|
END IF;
|
|
WHEN s181 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s189;
|
|
ELSE
|
|
next_state <= s181;
|
|
END IF;
|
|
WHEN s182 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s191;
|
|
ELSE
|
|
next_state <= s182;
|
|
END IF;
|
|
WHEN s183 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s187;
|
|
ELSE
|
|
next_state <= s183;
|
|
END IF;
|
|
WHEN s184 =>
|
|
next_state <= FETCH;
|
|
WHEN s185 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s190;
|
|
ELSE
|
|
next_state <= s185;
|
|
END IF;
|
|
WHEN s186 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s188;
|
|
ELSE
|
|
next_state <= s186;
|
|
END IF;
|
|
WHEN s187 =>
|
|
next_state <= FETCH;
|
|
WHEN s188 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s192;
|
|
ELSE
|
|
next_state <= s188;
|
|
END IF;
|
|
WHEN s189 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s191;
|
|
ELSE
|
|
next_state <= s189;
|
|
END IF;
|
|
WHEN s190 =>
|
|
next_state <= FETCH;
|
|
WHEN s191 =>
|
|
next_state <= s193;
|
|
WHEN s192 =>
|
|
next_state <= s193;
|
|
WHEN s193 =>
|
|
next_state <= FETCH;
|
|
WHEN s377 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s381;
|
|
ELSE
|
|
next_state <= s377;
|
|
END IF;
|
|
WHEN s381 =>
|
|
next_state <= FETCH;
|
|
WHEN s378 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s382;
|
|
ELSE
|
|
next_state <= s378;
|
|
END IF;
|
|
WHEN s382 =>
|
|
next_state <= FETCH;
|
|
WHEN s379 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s383;
|
|
ELSE
|
|
next_state <= s379;
|
|
END IF;
|
|
WHEN s383 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s384;
|
|
ELSE
|
|
next_state <= s383;
|
|
END IF;
|
|
WHEN s384 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s384;
|
|
END IF;
|
|
WHEN s380 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s385;
|
|
ELSE
|
|
next_state <= s380;
|
|
END IF;
|
|
WHEN s385 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s386;
|
|
ELSE
|
|
next_state <= s385;
|
|
END IF;
|
|
WHEN s386 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s386;
|
|
END IF;
|
|
WHEN s387 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s388;
|
|
ELSE
|
|
next_state <= s387;
|
|
END IF;
|
|
WHEN s388 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s389;
|
|
ELSE
|
|
next_state <= s388;
|
|
END IF;
|
|
WHEN s389 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s391;
|
|
ELSE
|
|
next_state <= s389;
|
|
END IF;
|
|
WHEN s391 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s392;
|
|
ELSE
|
|
next_state <= s391;
|
|
END IF;
|
|
WHEN s392 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s392;
|
|
END IF;
|
|
WHEN s390 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s393;
|
|
ELSE
|
|
next_state <= s390;
|
|
END IF;
|
|
WHEN s393 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s394;
|
|
ELSE
|
|
next_state <= s393;
|
|
END IF;
|
|
WHEN s394 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s395;
|
|
ELSE
|
|
next_state <= s394;
|
|
END IF;
|
|
WHEN s395 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s396;
|
|
ELSE
|
|
next_state <= s395;
|
|
END IF;
|
|
WHEN s396 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s396;
|
|
END IF;
|
|
WHEN s397 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s398;
|
|
ELSE
|
|
next_state <= s397;
|
|
END IF;
|
|
WHEN s398 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s399;
|
|
ELSE
|
|
next_state <= s398;
|
|
END IF;
|
|
WHEN s399 =>
|
|
next_state <= s400;
|
|
WHEN s400 =>
|
|
next_state <= s401;
|
|
WHEN s401 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s401;
|
|
END IF;
|
|
WHEN s526 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s527;
|
|
ELSE
|
|
next_state <= s526;
|
|
END IF;
|
|
WHEN s527 =>
|
|
next_state <= s528;
|
|
WHEN s528 =>
|
|
next_state <= s529;
|
|
WHEN s529 =>
|
|
next_state <= s531;
|
|
WHEN s530 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s530;
|
|
END IF;
|
|
WHEN s531 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s530;
|
|
ELSE
|
|
next_state <= s531;
|
|
END IF;
|
|
WHEN s544 =>
|
|
next_state <= s550;
|
|
WHEN s545 =>
|
|
next_state <= s546;
|
|
WHEN s546 =>
|
|
next_state <= s547;
|
|
WHEN s547 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s549;
|
|
ELSE
|
|
next_state <= s547;
|
|
END IF;
|
|
WHEN s549 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s549;
|
|
END IF;
|
|
WHEN s550 =>
|
|
next_state <= s545;
|
|
WHEN s404 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s404;
|
|
END IF;
|
|
WHEN s556 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s556;
|
|
END IF;
|
|
WHEN s557 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s557;
|
|
END IF;
|
|
WHEN s579 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s579;
|
|
END IF;
|
|
WHEN s201 =>
|
|
IF (rdy_i = '1' and
|
|
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
|
|
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
|
|
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
|
|
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
|
|
next_state <= s224;
|
|
ELSIF ((rdy_i = '1' and
|
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1' and
|
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1' and
|
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1' and
|
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"B5" OR
|
|
zw_REG_OP = X"B4" OR
|
|
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
|
|
zw_REG_OP = X"35" OR
|
|
zw_REG_OP = X"D5")) THEN
|
|
next_state <= s217;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"AD" OR
|
|
zw_REG_OP = X"AE" OR
|
|
zw_REG_OP = X"AC" OR
|
|
zw_REG_OP = X"4D" OR
|
|
zw_REG_OP = X"0D" OR
|
|
zw_REG_OP = X"2D" OR
|
|
zw_REG_OP = X"CD" OR
|
|
zw_REG_OP = X"EC" OR
|
|
zw_REG_OP = X"CC")) THEN
|
|
next_state <= s202;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"BD" OR
|
|
zw_REG_OP = X"BC" OR
|
|
zw_REG_OP = X"5D" OR
|
|
zw_REG_OP = X"1D" OR
|
|
zw_REG_OP = X"3D" OR
|
|
zw_REG_OP = X"DD")) THEN
|
|
next_state <= s210;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"B9" OR
|
|
zw_REG_OP = X"BE" OR
|
|
zw_REG_OP = X"59" OR
|
|
zw_REG_OP = X"19" OR
|
|
zw_REG_OP = X"39" OR
|
|
zw_REG_OP = X"D9")) THEN
|
|
next_state <= s211;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"B1" OR
|
|
zw_REG_OP = X"51" OR
|
|
zw_REG_OP = X"11" OR
|
|
zw_REG_OP = X"31" OR
|
|
zw_REG_OP = X"D1")) THEN
|
|
next_state <= s215;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"A1" OR
|
|
zw_REG_OP = X"41" OR
|
|
zw_REG_OP = X"01" OR
|
|
zw_REG_OP = X"21" OR
|
|
zw_REG_OP = X"C1")) THEN
|
|
next_state <= s218;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"B6") THEN
|
|
next_state <= s217;
|
|
ELSE
|
|
next_state <= s201;
|
|
END IF;
|
|
WHEN s202 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s224;
|
|
ELSE
|
|
next_state <= s202;
|
|
END IF;
|
|
WHEN s210 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s225;
|
|
ELSE
|
|
next_state <= s210;
|
|
END IF;
|
|
WHEN s211 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s225;
|
|
ELSE
|
|
next_state <= s211;
|
|
END IF;
|
|
WHEN s215 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s223;
|
|
ELSE
|
|
next_state <= s215;
|
|
END IF;
|
|
WHEN s217 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s224;
|
|
ELSE
|
|
next_state <= s217;
|
|
END IF;
|
|
WHEN s218 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s222;
|
|
ELSE
|
|
next_state <= s218;
|
|
END IF;
|
|
WHEN s222 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s202;
|
|
ELSE
|
|
next_state <= s222;
|
|
END IF;
|
|
WHEN s223 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s225;
|
|
ELSE
|
|
next_state <= s223;
|
|
END IF;
|
|
WHEN s224 =>
|
|
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s224;
|
|
END IF;
|
|
WHEN s225 =>
|
|
IF ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' AND
|
|
zw_b2(0) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= s224;
|
|
ELSE
|
|
next_state <= s225;
|
|
END IF;
|
|
WHEN s226 =>
|
|
IF (rdy_i = '1' and
|
|
(zw_REG_OP = X"C6" OR
|
|
zw_REG_OP = X"E6")) THEN
|
|
next_state <= s343;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"D6" OR
|
|
zw_REG_OP = X"F6")) THEN
|
|
next_state <= s247;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"CE" OR
|
|
zw_REG_OP = X"EE")) THEN
|
|
next_state <= s243;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"DE" OR
|
|
zw_REG_OP = X"FE")) THEN
|
|
next_state <= s244;
|
|
ELSE
|
|
next_state <= s226;
|
|
END IF;
|
|
WHEN s243 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s343;
|
|
ELSE
|
|
next_state <= s243;
|
|
END IF;
|
|
WHEN s244 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s344;
|
|
ELSE
|
|
next_state <= s244;
|
|
END IF;
|
|
WHEN s247 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s343;
|
|
ELSE
|
|
next_state <= s247;
|
|
END IF;
|
|
WHEN s344 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s343;
|
|
ELSE
|
|
next_state <= s344;
|
|
END IF;
|
|
WHEN s343 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s250;
|
|
ELSE
|
|
next_state <= s343;
|
|
END IF;
|
|
WHEN s250 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s251;
|
|
ELSE
|
|
next_state <= s250;
|
|
END IF;
|
|
WHEN s251 =>
|
|
next_state <= FETCH;
|
|
WHEN s351 =>
|
|
IF (rdy_i = '1' and
|
|
zw_REG_OP = X"24") THEN
|
|
next_state <= s361;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"2C") THEN
|
|
next_state <= s360;
|
|
ELSE
|
|
next_state <= s351;
|
|
END IF;
|
|
WHEN s361 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s361;
|
|
END IF;
|
|
WHEN s360 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s361;
|
|
ELSE
|
|
next_state <= s360;
|
|
END IF;
|
|
WHEN s403 =>
|
|
IF (rdy_i = '1' and
|
|
(zw_REG_OP = X"1E" or
|
|
zw_REG_OP = X"7E" or
|
|
zw_REG_OP = X"3E" or
|
|
zw_REG_OP = X"5E")) THEN
|
|
next_state <= s407;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"06" or
|
|
zw_REG_OP = X"66" or
|
|
zw_REG_OP = X"26" or
|
|
zw_REG_OP = X"46")) THEN
|
|
next_state <= s413;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"16" or
|
|
zw_REG_OP = X"76" or
|
|
zw_REG_OP = X"36" or
|
|
zw_REG_OP = X"56")) THEN
|
|
next_state <= s409;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"0E" or
|
|
zw_REG_OP = X"6E" or
|
|
zw_REG_OP = X"2E" or
|
|
zw_REG_OP = X"4E")) THEN
|
|
next_state <= s406;
|
|
ELSE
|
|
next_state <= s403;
|
|
END IF;
|
|
WHEN s406 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s413;
|
|
ELSE
|
|
next_state <= s406;
|
|
END IF;
|
|
WHEN s407 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s412;
|
|
ELSE
|
|
next_state <= s407;
|
|
END IF;
|
|
WHEN s409 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s413;
|
|
ELSE
|
|
next_state <= s409;
|
|
END IF;
|
|
WHEN s412 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s413;
|
|
ELSE
|
|
next_state <= s412;
|
|
END IF;
|
|
WHEN s413 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s416;
|
|
ELSE
|
|
next_state <= s413;
|
|
END IF;
|
|
WHEN s416 =>
|
|
IF (rdy_i = '1' and
|
|
(zw_REG_OP = X"06" or
|
|
zw_REG_OP = X"16" or
|
|
zw_REG_OP = X"0E" or
|
|
zw_REG_OP = X"1E")) THEN
|
|
next_state <= s418;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"46" or
|
|
zw_REG_OP = X"56" or
|
|
zw_REG_OP = X"4E" or
|
|
zw_REG_OP = X"5E")) THEN
|
|
next_state <= s418;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"26" or
|
|
zw_REG_OP = X"36" or
|
|
zw_REG_OP = X"2E" or
|
|
zw_REG_OP = X"3E")) THEN
|
|
next_state <= s418;
|
|
ELSIF (rdy_i = '1' and
|
|
(zw_REG_OP = X"66" or
|
|
zw_REG_OP = X"76" or
|
|
zw_REG_OP = X"6E" or
|
|
zw_REG_OP = X"7E")) THEN
|
|
next_state <= s418;
|
|
ELSE
|
|
next_state <= s416;
|
|
END IF;
|
|
WHEN s418 =>
|
|
next_state <= FETCH;
|
|
WHEN s510 =>
|
|
IF (rdy_i = '1' and
|
|
zw_REG_OP = X"65") THEN
|
|
next_state <= s565;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"69" and
|
|
reg_F(3) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"75") THEN
|
|
next_state <= s560;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"6D") THEN
|
|
next_state <= s553;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"7D") THEN
|
|
next_state <= s555;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"79") THEN
|
|
next_state <= s555;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"71") THEN
|
|
next_state <= s558;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"61") THEN
|
|
next_state <= s561;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"69" and
|
|
reg_F(3) = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s510;
|
|
END IF;
|
|
WHEN s553 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s565;
|
|
ELSE
|
|
next_state <= s553;
|
|
END IF;
|
|
WHEN s555 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s564;
|
|
ELSE
|
|
next_state <= s555;
|
|
END IF;
|
|
WHEN s558 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s566;
|
|
ELSE
|
|
next_state <= s558;
|
|
END IF;
|
|
WHEN s560 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s565;
|
|
ELSE
|
|
next_state <= s560;
|
|
END IF;
|
|
WHEN s561 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s563;
|
|
ELSE
|
|
next_state <= s561;
|
|
END IF;
|
|
WHEN s563 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s553;
|
|
ELSE
|
|
next_state <= s563;
|
|
END IF;
|
|
WHEN s564 =>
|
|
IF (rdy_i = '1' AND
|
|
zw_b2(0) = '0' and
|
|
reg_F(3) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' AND
|
|
zw_b2(0) = '0' and
|
|
reg_F(3) = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= s565;
|
|
ELSE
|
|
next_state <= s564;
|
|
END IF;
|
|
WHEN s565 =>
|
|
IF (rdy_i = '1' and
|
|
reg_F(3) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
reg_F(3) = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s565;
|
|
END IF;
|
|
WHEN s566 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s564;
|
|
ELSE
|
|
next_state <= s566;
|
|
END IF;
|
|
WHEN s266 =>
|
|
IF (rdy_i = '1' and (
|
|
(reg_F(0) = '1' and zw_REG_OP = X"90") or
|
|
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
|
|
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
|
|
(reg_F(7) = '0' and zw_REG_OP = X"30") or
|
|
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
|
|
(reg_F(7) = '1' and zw_REG_OP = X"10") or
|
|
(reg_F(6) = '1' and zw_REG_OP = X"50") or
|
|
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= s301;
|
|
ELSE
|
|
next_state <= s266;
|
|
END IF;
|
|
WHEN s301 =>
|
|
IF (rdy_i = '1' and
|
|
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= s302;
|
|
ELSE
|
|
next_state <= s301;
|
|
END IF;
|
|
WHEN s302 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s302;
|
|
END IF;
|
|
WHEN RES =>
|
|
next_state <= s544;
|
|
WHEN s511 =>
|
|
IF (rdy_i = '1' and
|
|
zw_REG_OP = X"E5") THEN
|
|
next_state <= s574;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"E9" and
|
|
reg_F(3) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"F5") THEN
|
|
next_state <= s569;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"ED") THEN
|
|
next_state <= s559;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"FD") THEN
|
|
next_state <= s562;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"F9") THEN
|
|
next_state <= s567;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"F1") THEN
|
|
next_state <= s568;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"E1") THEN
|
|
next_state <= s570;
|
|
ELSIF (rdy_i = '1' and
|
|
zw_REG_OP = X"E9" and
|
|
reg_F(3) = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s511;
|
|
END IF;
|
|
WHEN s559 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s574;
|
|
ELSE
|
|
next_state <= s559;
|
|
END IF;
|
|
WHEN s562 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s573;
|
|
ELSE
|
|
next_state <= s562;
|
|
END IF;
|
|
WHEN s567 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s573;
|
|
ELSE
|
|
next_state <= s567;
|
|
END IF;
|
|
WHEN s568 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s571;
|
|
ELSE
|
|
next_state <= s568;
|
|
END IF;
|
|
WHEN s569 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s574;
|
|
ELSE
|
|
next_state <= s569;
|
|
END IF;
|
|
WHEN s570 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s572;
|
|
ELSE
|
|
next_state <= s570;
|
|
END IF;
|
|
WHEN s571 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s573;
|
|
ELSE
|
|
next_state <= s571;
|
|
END IF;
|
|
WHEN s572 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s559;
|
|
ELSE
|
|
next_state <= s572;
|
|
END IF;
|
|
WHEN s573 =>
|
|
IF (rdy_i = '1' AND
|
|
zw_b2(0) = '0' and
|
|
reg_F(3) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' AND
|
|
zw_b2(0) = '0' and
|
|
reg_F(3) = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1') THEN
|
|
next_state <= s574;
|
|
ELSE
|
|
next_state <= s573;
|
|
END IF;
|
|
WHEN s574 =>
|
|
IF (rdy_i = '1' and
|
|
reg_F(3) = '0') THEN
|
|
next_state <= FETCH;
|
|
ELSIF (rdy_i = '1' and
|
|
reg_F(3) = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s574;
|
|
END IF;
|
|
WHEN s548 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s551;
|
|
ELSE
|
|
next_state <= s548;
|
|
END IF;
|
|
WHEN s551 =>
|
|
next_state <= s552;
|
|
WHEN s552 =>
|
|
next_state <= s576;
|
|
WHEN s575 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s577;
|
|
ELSE
|
|
next_state <= s575;
|
|
END IF;
|
|
WHEN s576 =>
|
|
IF (NMI_i = '1') THEN
|
|
next_state <= s578;
|
|
ELSE
|
|
next_state <= s575;
|
|
END IF;
|
|
WHEN s577 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= FETCH;
|
|
ELSE
|
|
next_state <= s577;
|
|
END IF;
|
|
WHEN s578 =>
|
|
IF (rdy_i = '1') THEN
|
|
next_state <= s577;
|
|
ELSE
|
|
next_state <= s578;
|
|
END IF;
|
|
WHEN OTHERS =>
|
|
next_state <= RES;
|
|
END CASE;
|
|
END PROCESS nextstate_proc;
|
|
|
|
-----------------------------------------------------------------
|
|
output_proc : PROCESS (
|
|
adr_nxt_pc_i,
|
|
adr_pc_i,
|
|
adr_sp_i,
|
|
current_state,
|
|
d_alu_i,
|
|
d_i,
|
|
d_regs_out_i,
|
|
irq_n_i,
|
|
nmi_i,
|
|
q_a_i,
|
|
q_x_i,
|
|
q_y_i,
|
|
rdy_i,
|
|
reg_F,
|
|
reg_sel_pc_in,
|
|
reg_sel_pc_val,
|
|
reg_sel_rb_in,
|
|
reg_sel_rb_out,
|
|
reg_sel_reg,
|
|
reg_sel_sp_as,
|
|
reg_sel_sp_in,
|
|
sig_PC,
|
|
zw_ALU,
|
|
zw_ALU1,
|
|
zw_ALU2,
|
|
zw_ALU3,
|
|
zw_ALU4,
|
|
zw_ALU5,
|
|
zw_ALU6,
|
|
zw_REG_OP,
|
|
zw_b1,
|
|
zw_b2,
|
|
zw_b3,
|
|
zw_b4
|
|
)
|
|
-----------------------------------------------------------------
|
|
BEGIN
|
|
-- Default Assignment
|
-- Default Assignment
|
a_o <= sig_PC;
|
a_o <= sig_PC;
|
adr_o <= X"0000";
|
adr_o <= X"0000";
|
ch_a_o <= X"00";
|
ch_a_o <= X"00";
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
d_regs_in_o <= X"00";
|
d_regs_in_o <= X"00";
|
|
int_fetch_o <= '0';
|
|
int_reg_2flag_o <= reg_F(2);
|
ld_o <= "00";
|
ld_o <= "00";
|
ld_pc_o <= '0';
|
ld_pc_o <= '0';
|
ld_sp_o <= '0';
|
ld_sp_o <= '0';
|
load_regs_o <= '0';
|
load_regs_o <= '0';
|
offset_o <= X"0000";
|
offset_o <= X"0000";
|
| Line 3314... |
Line 2103... |
sig_D_OUT <= X"00";
|
sig_D_OUT <= X"00";
|
sig_RD <= '1';
|
sig_RD <= '1';
|
sig_RWn <= '1';
|
sig_RWn <= '1';
|
sig_SYNC <= '0';
|
sig_SYNC <= '0';
|
sig_WR <= '0';
|
sig_WR <= '0';
|
zw_ALU <= '0' & X"00";
|
zw_alu <= "00" & X"00";
|
zw_ALU1 <= '0' & X"0";
|
zw_alu1 <= "00" & X"00";
|
zw_ALU2 <= '0' & X"0";
|
zw_alu2 <= "00" & X"00";
|
zw_ALU3 <= '0' & X"0";
|
zw_alu3 <= "00" & X"00";
|
zw_ALU4 <= '0' & X"0";
|
zw_alu4 <= "00" & X"00";
|
zw_ALU5 <= X"0";
|
zw_ninebits4 <= '0' & X"00";
|
zw_ALU6 <= X"0";
|
|
|
|
-- Combined Actions
|
-- Combined Actions
|
CASE current_state IS
|
case current_state is
|
WHEN FETCH =>
|
when FETCH =>
|
sig_RWn <= '1';
|
sig_RWn <= '1';
|
sig_RD <= '1';
|
sig_RD <= '1';
|
sig_SYNC <= NOT (rdy_i);
|
sig_SYNC <= NOT (rdy_i);
|
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
|
int_fetch_o <= '1';
|
ELSIF ((irq_n_i = '0' and
|
if ((d_i = X"00") and (rdy_i = '1')) then
|
reg_F(2) = '0') AND (rdy_i = '1')) THEN
|
ld_o <= "11";
|
ELSIF ((d_i = X"69" or
|
ld_pc_o <= '1';
|
|
next_state <= s0901;
|
|
elsif ((nmi_i = '1') and (rdy_i = '1')) then
|
|
next_state <= s2701;
|
|
elsif ((irq_n_i = '0' and
|
|
reg_F(2) = '0') and (rdy_i = '1')) then
|
|
next_state <= s2701;
|
|
elsif ((d_i = X"69" or
|
d_i = X"65" or
|
d_i = X"65" or
|
d_i = X"75" or
|
d_i = X"75" or
|
d_i = X"6D" or
|
d_i = X"6D" or
|
d_i = X"7D" or
|
d_i = X"7D" or
|
d_i = X"79" or
|
d_i = X"79" or
|
d_i = X"61" or
|
d_i = X"61" or
|
d_i = X"71") AND (rdy_i = '1')) THEN
|
d_i = X"71") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"06" or
|
next_state <= s0501;
|
|
elsif ((d_i = X"06" or
|
d_i = X"16" or
|
d_i = X"16" or
|
d_i = X"0E" or
|
d_i = X"0E" or
|
d_i = X"1E") AND (rdy_i = '1')) THEN
|
d_i = X"1E") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"90" or
|
next_state <= s0601;
|
|
elsif ((d_i = X"90" or
|
d_i = X"B0" or
|
d_i = X"B0" or
|
d_i = X"F0" or
|
d_i = X"F0" or
|
d_i = X"30" or
|
d_i = X"30" or
|
d_i = X"D0" or
|
d_i = X"D0" or
|
d_i = X"10" or
|
d_i = X"10" or
|
d_i = X"50" or
|
d_i = X"50" or
|
d_i = X"70") AND (rdy_i = '1')) THEN
|
d_i = X"70") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"24" or
|
next_state <= s0701;
|
d_i = X"2C") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"24" or
|
|
d_i = X"2C") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
|
next_state <= s0801;
|
|
elsif ((d_i = X"18") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
|
next_state <= s1001;
|
|
elsif ((d_i = X"D8") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
|
next_state <= s1101;
|
|
elsif ((d_i = X"58") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
|
next_state <= s1201;
|
|
elsif ((d_i = X"B8") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
|
next_state <= s1301;
|
ld_o <= "11";
|
elsif ((d_i = X"E0" or
|
ld_pc_o <= '1';
|
|
ELSIF ((d_i = X"E0" or
|
|
d_i = X"E4" or
|
d_i = X"E4" or
|
d_i = X"EC") AND (rdy_i = '1')) THEN
|
d_i = X"EC") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"C0" or
|
next_state <= s1801;
|
|
elsif ((d_i = X"C0" or
|
d_i = X"C4" or
|
d_i = X"C4" or
|
d_i = X"CC") AND (rdy_i = '1')) THEN
|
d_i = X"CC") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"C6" or
|
next_state <= s1801;
|
|
elsif ((d_i = X"C6" or
|
d_i = X"D6" or
|
d_i = X"D6" or
|
d_i = X"CE" or
|
d_i = X"CE" or
|
d_i = X"DE") AND (rdy_i = '1')) THEN
|
d_i = X"DE") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
|
next_state <= s1401;
|
|
elsif ((d_i = X"CA") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
|
next_state <= s1501;
|
|
elsif ((d_i = X"88") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"49" or
|
next_state <= s1501;
|
|
elsif ((d_i = X"49" or
|
d_i = X"45" or
|
d_i = X"45" or
|
d_i = X"55" or
|
d_i = X"55" or
|
d_i = X"4D" or
|
d_i = X"4D" or
|
d_i = X"5D" or
|
d_i = X"5D" or
|
d_i = X"59" or
|
d_i = X"59" or
|
| Line 3429... |
Line 2234... |
d_i = X"D5" or
|
d_i = X"D5" or
|
d_i = X"CD" or
|
d_i = X"CD" or
|
d_i = X"DD" or
|
d_i = X"DD" or
|
d_i = X"D9" or
|
d_i = X"D9" or
|
d_i = X"C1" or
|
d_i = X"C1" or
|
d_i = X"D1") AND (rdy_i = '1')) THEN
|
d_i = X"D1") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"E6" or
|
next_state <= s1801;
|
|
elsif ((d_i = X"E6" or
|
d_i = X"F6" or
|
d_i = X"F6" or
|
d_i = X"EE" or
|
d_i = X"EE" or
|
d_i = X"FE") AND (rdy_i = '1')) THEN
|
d_i = X"FE") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
|
next_state <= s1401;
|
|
elsif ((d_i = X"E8") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
|
next_state <= s1501;
|
|
elsif ((d_i = X"C8") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"4C" or
|
next_state <= s1501;
|
d_i = X"6C") AND (rdy_i = '1')) THEN
|
elsif ((d_i = X"4C" or
|
|
d_i = X"6C") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
|
next_state <= s1601;
|
|
elsif ((d_i = X"20") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"A9" or
|
next_state <= s1701;
|
|
elsif ((d_i = X"A9" or
|
d_i = X"A5" or
|
d_i = X"A5" or
|
d_i = X"B5" or
|
d_i = X"B5" or
|
d_i = X"AD" or
|
d_i = X"AD" or
|
d_i = X"BD" or
|
d_i = X"BD" or
|
d_i = X"B9" or
|
d_i = X"B9" or
|
d_i = X"A1" or
|
d_i = X"A1" or
|
d_i = X"B1") AND (rdy_i = '1')) THEN
|
d_i = X"B1") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"A2" or
|
next_state <= s1801;
|
|
elsif ((d_i = X"A2" or
|
d_i = X"A6" or
|
d_i = X"A6" or
|
d_i = X"B6" or
|
d_i = X"B6" or
|
d_i = X"AE" or
|
d_i = X"AE" or
|
d_i = X"BE") AND (rdy_i = '1')) THEN
|
d_i = X"BE") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"A0" or
|
next_state <= s1801;
|
|
elsif ((d_i = X"A0" or
|
d_i = X"A4" or
|
d_i = X"A4" or
|
d_i = X"B4" or
|
d_i = X"B4" or
|
d_i = X"AC" or
|
d_i = X"AC" or
|
d_i = X"BC") AND (rdy_i = '1')) THEN
|
d_i = X"BC") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"46" or
|
next_state <= s1801;
|
|
elsif ((d_i = X"46" or
|
d_i = X"56" or
|
d_i = X"56" or
|
d_i = X"4E" or
|
d_i = X"4E" or
|
d_i = X"5E") AND (rdy_i = '1')) THEN
|
d_i = X"5E") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
|
next_state <= s0601;
|
|
elsif ((d_i = X"EA") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
|
next_state <= s0001;
|
|
elsif ((d_i = X"48") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
|
next_state <= s1901;
|
|
elsif ((d_i = X"08") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
|
next_state <= s2001;
|
|
elsif ((d_i = X"68") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
|
next_state <= s2101;
|
|
elsif ((d_i = X"28") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"26" or
|
next_state <= s2201;
|
|
elsif ((d_i = X"26" or
|
d_i = X"36" or
|
d_i = X"36" or
|
d_i = X"2E" or
|
d_i = X"2E" or
|
d_i = X"3E") AND (rdy_i = '1')) THEN
|
d_i = X"3E") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"66" or
|
next_state <= s0601;
|
|
elsif ((d_i = X"66" or
|
d_i = X"76" or
|
d_i = X"76" or
|
d_i = X"6E" or
|
d_i = X"6E" or
|
d_i = X"7E") AND (rdy_i = '1')) THEN
|
d_i = X"7E") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
|
next_state <= s0601;
|
|
elsif ((d_i = X"40") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
|
next_state <= s2301;
|
|
elsif ((d_i = X"60") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"E9" or
|
next_state <= s2401;
|
|
elsif ((d_i = X"E9" or
|
d_i = X"E5" or
|
d_i = X"E5" or
|
d_i = X"F5" or
|
d_i = X"F5" or
|
d_i = X"ED" or
|
d_i = X"ED" or
|
d_i = X"FD" or
|
d_i = X"FD" or
|
d_i = X"F9" or
|
d_i = X"F9" or
|
d_i = X"E1" or
|
d_i = X"E1" or
|
d_i = X"F1") AND (rdy_i = '1')) THEN
|
d_i = X"F1") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
|
next_state <= s2501;
|
|
elsif ((d_i = X"38") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
|
next_state <= s0101;
|
|
elsif ((d_i = X"F8") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
|
next_state <= s0201;
|
|
elsif ((d_i = X"78") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"85" or
|
next_state <= s0301;
|
|
elsif ((d_i = X"85" or
|
d_i = X"95" or
|
d_i = X"95" or
|
d_i = X"8D" or
|
d_i = X"8D" or
|
d_i = X"9D" or
|
d_i = X"9D" or
|
d_i = X"99" or
|
d_i = X"99" or
|
d_i = X"81" or
|
d_i = X"81" or
|
d_i = X"91") AND (rdy_i = '1')) THEN
|
d_i = X"91") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"86" or
|
next_state <= s2601;
|
|
elsif ((d_i = X"86" or
|
d_i = X"96" or
|
d_i = X"96" or
|
d_i = X"8E") AND (rdy_i = '1')) THEN
|
d_i = X"8E") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"84" or
|
next_state <= s2601;
|
|
elsif ((d_i = X"84" or
|
d_i = X"94" or
|
d_i = X"94" or
|
d_i = X"8C") AND (rdy_i = '1')) THEN
|
d_i = X"8C") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
|
next_state <= s2601;
|
|
elsif ((d_i = X"AA") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
|
next_state <= s0401;
|
|
elsif ((d_i = X"0A") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
|
next_state <= s2801;
|
|
elsif ((d_i = X"4A") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
|
next_state <= s2901;
|
|
elsif ((d_i = X"2A") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
|
next_state <= s3001;
|
|
elsif ((d_i = X"6A") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
|
next_state <= s3101;
|
|
elsif ((d_i = X"A8") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
|
next_state <= s0401;
|
|
elsif ((d_i = X"98") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
|
next_state <= s0401;
|
|
elsif ((d_i = X"BA") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
|
next_state <= s0401;
|
|
elsif ((d_i = X"8A") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
|
next_state <= s0401;
|
|
elsif ((d_i = X"9A") and (rdy_i = '1')) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1') THEN
|
next_state <= s0401;
|
|
elsif (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s0001;
|
WHEN s1 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= FETCH;
|
|
end if;
|
|
when s0001 =>
|
|
if (rdy_i = '1') then
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s2 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0001;
|
|
end if;
|
|
when s0101 =>
|
|
if (rdy_i = '1') then
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s5 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0101;
|
|
end if;
|
|
when s0201 =>
|
|
if (rdy_i = '1') then
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s3 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0201;
|
|
end if;
|
|
when s0301 =>
|
|
if (rdy_i = '1') then
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s4 =>
|
else
|
IF (rdy_i = '1' and
|
next_state <= s0301;
|
zw_REG_OP = X"9A") THEN
|
end if;
|
|
when s0401 =>
|
|
if (rdy_i = '1' and
|
|
zw_REG_OP = X"9A") then
|
adr_o <= X"01" & d_regs_out_i;
|
adr_o <= X"01" & d_regs_out_i;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
zw_REG_OP = X"BA") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"BA") then
|
d_regs_in_o <= adr_sp_i (7 downto 0);
|
d_regs_in_o <= adr_sp_i (7 downto 0);
|
ch_a_o <= adr_sp_i (7 downto 0);
|
ch_a_o <= adr_sp_i (7 downto 0);
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1') THEN
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1') then
|
ch_a_o <= d_regs_out_i;
|
ch_a_o <= d_regs_out_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s12 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0401;
|
sig_SYNC <= '1';
|
end if;
|
END IF;
|
when s1001 =>
|
WHEN s16 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
next_state <= FETCH;
|
END IF;
|
else
|
WHEN s17 =>
|
next_state <= s1001;
|
IF (rdy_i = '1') THEN
|
end if;
|
sig_SYNC <= '1';
|
when s1101 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s24 =>
|
sig_SYNC <= '1';
|
IF (rdy_i = '1') THEN
|
next_state <= FETCH;
|
sig_SYNC <= '1';
|
else
|
END IF;
|
next_state <= s1101;
|
WHEN s25 =>
|
end if;
|
IF (rdy_i = '1') THEN
|
when s1201 =>
|
|
if (rdy_i = '1') then
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s1201;
|
|
end if;
|
|
when s1301 =>
|
|
if (rdy_i = '1') then
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s1301;
|
|
end if;
|
|
when s1501 =>
|
|
if (rdy_i = '1') then
|
d_regs_in_o <= d_alu_i;
|
d_regs_in_o <= d_alu_i;
|
ch_a_o <= d_regs_out_i;
|
ch_a_o <= d_regs_out_i;
|
ch_b_o <= zw_b4;
|
ch_b_o <= zw_b4;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s273 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1501;
|
|
end if;
|
|
when s1601 =>
|
|
if (rdy_i = '1' and
|
|
zw_REG_OP = X"4C") then
|
|
ld_pc_o <= '1';
|
|
next_state <= s1604;
|
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"6C") then
|
|
next_state <= s1602;
|
|
else
|
|
next_state <= s1601;
|
|
end if;
|
|
when s1602 =>
|
|
if (rdy_i = '1') then
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1603;
|
WHEN s307 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1602;
|
|
end if;
|
|
when s1603 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s1604;
|
|
else
|
|
next_state <= s1603;
|
|
end if;
|
|
when s1604 =>
|
|
if (rdy_i = '1') then
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s177 =>
|
else
|
IF (rdy_i = '1' and
|
next_state <= s1604;
|
|
end if;
|
|
when s2601 =>
|
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"85" OR
|
(zw_REG_OP = X"85" OR
|
zw_REG_OP = X"86" OR
|
zw_REG_OP = X"86" OR
|
zw_REG_OP = X"84")) THEN
|
zw_REG_OP = X"84")) then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= d_regs_out_i;
|
sig_D_OUT <= d_regs_out_i;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s2611;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"95" OR
|
(zw_REG_OP = X"95" OR
|
zw_REG_OP = X"94")) THEN
|
zw_REG_OP = X"94")) then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2602;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"8D" OR
|
(zw_REG_OP = X"8D" OR
|
zw_REG_OP = X"8E" OR
|
zw_REG_OP = X"8E" OR
|
zw_REG_OP = X"8C")) THEN
|
zw_REG_OP = X"8C")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s2603;
|
zw_REG_OP = X"9D") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"9D") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2604;
|
zw_REG_OP = X"99") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"99") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2604;
|
zw_REG_OP = X"91") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"91") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ELSIF (rdy_i = '1' and
|
next_state <= s2605;
|
zw_REG_OP = X"81") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"81") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2606;
|
zw_REG_OP = X"96") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"96") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
END IF;
|
next_state <= s2602;
|
WHEN s180 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2601;
|
ch_a_o <= d_i;
|
end if;
|
ch_b_o <= "0000000" & zw_b2(0);
|
when s2605 =>
|
ld_o <= "11";
|
if (rdy_i = '1') then
|
ld_pc_o <= '1';
|
|
END IF;
|
|
WHEN s181 =>
|
|
IF (rdy_i = '1') THEN
|
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
END IF;
|
next_state <= s2608;
|
WHEN s182 =>
|
else
|
sig_RWn <= '1';
|
next_state <= s2605;
|
sig_RD <= '1';
|
end if;
|
IF (rdy_i = '1') THEN
|
when s2604 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= "0000000" & zw_b2(0);
|
ch_b_o <= "0000000" & zw_b2(0);
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2609;
|
WHEN s183 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2604;
|
|
end if;
|
|
when s2603 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= d_regs_out_i;
|
sig_D_OUT <= d_regs_out_i;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2611;
|
WHEN s184 =>
|
else
|
sig_SYNC <= '1';
|
next_state <= s2603;
|
WHEN s185 =>
|
end if;
|
IF (rdy_i = '1') THEN
|
when s2602 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= d_regs_out_i;
|
sig_D_OUT <= d_regs_out_i;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2611;
|
WHEN s187 =>
|
else
|
sig_SYNC <= '1';
|
next_state <= s2602;
|
WHEN s188 =>
|
end if;
|
IF (rdy_i = '1') THEN
|
when s2606 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2607;
|
|
else
|
|
next_state <= s2606;
|
|
end if;
|
|
when s2607 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= zw_b1;
|
ch_a_o <= zw_b1;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
END IF;
|
next_state <= s2610;
|
WHEN s189 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2607;
|
|
end if;
|
|
when s2608 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= "0000000" & zw_b2(0);
|
ch_b_o <= "0000000" & zw_b2(0);
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2609;
|
WHEN s190 =>
|
else
|
sig_SYNC <= '1';
|
next_state <= s2608;
|
WHEN s191 =>
|
end if;
|
|
when s2609 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= d_regs_out_i;
|
sig_D_OUT <= d_regs_out_i;
|
WHEN s192 =>
|
next_state <= s2611;
|
|
else
|
|
next_state <= s2609;
|
|
end if;
|
|
when s2610 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= d_regs_out_i;
|
sig_D_OUT <= d_regs_out_i;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
WHEN s193 =>
|
next_state <= s2611;
|
|
else
|
|
next_state <= s2610;
|
|
end if;
|
|
when s2611 =>
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
WHEN s377 =>
|
next_state <= FETCH;
|
IF (rdy_i = '1') THEN
|
when s1901 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= q_a_i;
|
sig_D_OUT <= q_a_i;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s1902;
|
WHEN s381 =>
|
else
|
|
next_state <= s1901;
|
|
end if;
|
|
when s1902 =>
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
WHEN s378 =>
|
next_state <= FETCH;
|
IF (rdy_i = '1') THEN
|
when s2001 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= reg_F;
|
sig_D_OUT <= reg_F OR X"30";
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2002;
|
WHEN s382 =>
|
else
|
|
next_state <= s2001;
|
|
end if;
|
|
when s2002 =>
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
WHEN s379 =>
|
next_state <= FETCH;
|
IF (rdy_i = '1') THEN
|
when s2101 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2102;
|
WHEN s384 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2101;
|
|
end if;
|
|
when s2102 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2103;
|
|
else
|
|
next_state <= s2102;
|
|
end if;
|
|
when s2103 =>
|
|
if (rdy_i = '1') then
|
d_regs_in_o <= d_i;
|
d_regs_in_o <= d_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s380 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2103;
|
|
end if;
|
|
when s2201 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2202;
|
WHEN s386 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2201;
|
sig_SYNC <= '1';
|
end if;
|
END IF;
|
when s2202 =>
|
WHEN s387 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
next_state <= s2203;
|
|
else
|
|
next_state <= s2202;
|
|
end if;
|
|
when s2203 =>
|
|
if (rdy_i = '1') then
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s2203;
|
|
end if;
|
|
when s2301 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2302;
|
WHEN s388 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2301;
|
|
end if;
|
|
when s2302 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2303;
|
WHEN s389 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2302;
|
|
end if;
|
|
when s2303 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2304;
|
WHEN s392 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2303;
|
|
end if;
|
|
when s2304 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2305;
|
|
else
|
|
next_state <= s2304;
|
|
end if;
|
|
when s2305 =>
|
|
if (rdy_i = '1') then
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s390 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2305;
|
|
end if;
|
|
when s2401 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2402;
|
WHEN s393 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2401;
|
|
end if;
|
|
when s2402 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
END IF;
|
next_state <= s2403;
|
WHEN s395 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2402;
|
|
end if;
|
|
when s2403 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2404;
|
|
else
|
|
next_state <= s2403;
|
|
end if;
|
|
when s2404 =>
|
|
if (rdy_i = '1') then
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2405;
|
WHEN s396 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2404;
|
sig_SYNC <= '1';
|
end if;
|
END IF;
|
when s2405 =>
|
WHEN s397 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s2405;
|
|
end if;
|
|
when s1701 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1702;
|
WHEN s398 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1701;
|
|
end if;
|
|
when s1702 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= adr_pc_i (15 downto 8);
|
sig_D_OUT <= adr_pc_i (15 downto 8);
|
END IF;
|
next_state <= s1703;
|
WHEN s399 =>
|
else
|
|
next_state <= s1702;
|
|
end if;
|
|
when s1703 =>
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= adr_pc_i (7 downto 0);
|
sig_D_OUT <= adr_pc_i (7 downto 0);
|
WHEN s401 =>
|
next_state <= s1704;
|
IF (rdy_i = '1') THEN
|
when s1704 =>
|
|
next_state <= s1705;
|
|
when s1705 =>
|
|
if (rdy_i = '1') then
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s526 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1705;
|
|
end if;
|
|
when s0901 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= adr_pc_i (15 downto 8);
|
sig_D_OUT <= adr_nxt_pc_i (15 downto 8);
|
END IF;
|
next_state <= s0902;
|
WHEN s527 =>
|
else
|
|
next_state <= s0901;
|
|
end if;
|
|
when s0902 =>
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= adr_pc_i (7 downto 0);
|
sig_D_OUT <= adr_pc_i (7 downto 0);
|
WHEN s528 =>
|
next_state <= s0903;
|
|
when s0903 =>
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= reg_F OR X"10";
|
sig_D_OUT <= reg_F OR
|
WHEN s530 =>
|
("001" & '1' & X"0");
|
IF (rdy_i = '1') THEN
|
next_state <= s0904;
|
adr_o <= d_i & zw_b1;
|
when s9901 =>
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
|
sig_SYNC <= '1';
|
|
END IF;
|
|
WHEN s544 =>
|
|
ld_o <= "11";
|
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
WHEN s545 =>
|
if (rdy_i = '1') then
|
adr_o <= X"FFFB";
|
|
ld_o <= "11";
|
ld_o <= "11";
|
|
next_state <= s9902;
|
|
else
|
|
next_state <= s9901;
|
|
end if;
|
|
when s9903 =>
|
|
adr_o <= X"FFFB";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
WHEN s546 =>
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
|
next_state <= s9904;
|
|
else
|
|
next_state <= s9903;
|
|
end if;
|
|
when s9904 =>
|
|
ld_pc_o <= '1';
|
|
if (rdy_i = '1') then
|
|
ld_o <= "11";
|
|
next_state <= s9905;
|
|
else
|
|
next_state <= s9904;
|
|
end if;
|
|
when s9905 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s9906;
|
|
else
|
|
next_state <= s9905;
|
|
end if;
|
|
when s9906 =>
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
WHEN s549 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s550 =>
|
else
|
ld_o <= "11";
|
next_state <= s9906;
|
|
end if;
|
|
when s9902 =>
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
WHEN s404 =>
|
if (rdy_i = '1') then
|
IF (rdy_i = '1') THEN
|
ld_o <= "11";
|
|
next_state <= s9903;
|
|
else
|
|
next_state <= s9902;
|
|
end if;
|
|
when s2801 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= q_a_i (6 downto 0) & '0';
|
ch_a_o <= q_a_i (6 downto 0) & '0';
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
d_regs_in_o <= q_a_i (6 downto 0) & '0';
|
d_regs_in_o <= q_a_i (6 downto 0) & '0';
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s556 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2801;
|
|
end if;
|
|
when s2901 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= '0' & q_a_i (7 downto 1);
|
ch_a_o <= '0' & q_a_i (7 downto 1);
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
d_regs_in_o <= '0' & q_a_i (7 downto 1);
|
d_regs_in_o <= '0' & q_a_i (7 downto 1);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s557 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2901;
|
|
end if;
|
|
when s3001 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
|
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
|
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s579 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s3001;
|
|
end if;
|
|
when s3101 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
|
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
|
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s201 =>
|
else
|
IF (rdy_i = '1' and
|
next_state <= s3101;
|
|
end if;
|
|
when s1801 =>
|
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
|
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
|
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
|
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
|
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
|
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
|
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
|
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF ((rdy_i = '1' and
|
next_state <= s1810;
|
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= d_i OR q_a_i;
|
d_regs_in_o <= d_i OR q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i OR q_a_i;
|
ch_a_o <= d_i OR q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1' and
|
next_state <= FETCH;
|
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= d_i XOR q_a_i;
|
d_regs_in_o <= d_i XOR q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i XOR q_a_i;
|
ch_a_o <= d_i XOR q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1' and
|
next_state <= FETCH;
|
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= d_i AND q_a_i;
|
d_regs_in_o <= d_i AND q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i AND q_a_i;
|
ch_a_o <= d_i AND q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1' and
|
next_state <= FETCH;
|
|
elsif ((rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
|
zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1;
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
|
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= d_i;
|
d_regs_in_o <= d_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"B5" OR
|
(zw_REG_OP = X"B5" OR
|
zw_REG_OP = X"B4" OR
|
zw_REG_OP = X"B4" OR
|
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
|
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
|
zw_REG_OP = X"35" OR
|
zw_REG_OP = X"35" OR
|
zw_REG_OP = X"D5")) THEN
|
zw_REG_OP = X"D5")) then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s1802;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"AD" OR
|
(zw_REG_OP = X"AD" OR
|
zw_REG_OP = X"AE" OR
|
zw_REG_OP = X"AE" OR
|
zw_REG_OP = X"AC" OR
|
zw_REG_OP = X"AC" OR
|
zw_REG_OP = X"4D" OR
|
zw_REG_OP = X"4D" OR
|
zw_REG_OP = X"0D" OR
|
zw_REG_OP = X"0D" OR
|
zw_REG_OP = X"2D" OR
|
zw_REG_OP = X"2D" OR
|
zw_REG_OP = X"CD" OR
|
zw_REG_OP = X"CD" OR
|
zw_REG_OP = X"EC" OR
|
zw_REG_OP = X"EC" OR
|
zw_REG_OP = X"CC")) THEN
|
zw_REG_OP = X"CC")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s1803;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"BD" OR
|
(zw_REG_OP = X"BD" OR
|
zw_REG_OP = X"BC" OR
|
zw_REG_OP = X"BC" OR
|
zw_REG_OP = X"5D" OR
|
zw_REG_OP = X"5D" OR
|
zw_REG_OP = X"1D" OR
|
zw_REG_OP = X"1D" OR
|
zw_REG_OP = X"3D" OR
|
zw_REG_OP = X"3D" OR
|
zw_REG_OP = X"DD")) THEN
|
zw_REG_OP = X"DD")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s1805;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"B9" OR
|
(zw_REG_OP = X"B9" OR
|
zw_REG_OP = X"BE" OR
|
zw_REG_OP = X"BE" OR
|
zw_REG_OP = X"59" OR
|
zw_REG_OP = X"59" OR
|
zw_REG_OP = X"19" OR
|
zw_REG_OP = X"19" OR
|
zw_REG_OP = X"39" OR
|
zw_REG_OP = X"39" OR
|
zw_REG_OP = X"D9")) THEN
|
zw_REG_OP = X"D9")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s1805;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"B1" OR
|
(zw_REG_OP = X"B1" OR
|
zw_REG_OP = X"51" OR
|
zw_REG_OP = X"51" OR
|
zw_REG_OP = X"11" OR
|
zw_REG_OP = X"11" OR
|
zw_REG_OP = X"31" OR
|
zw_REG_OP = X"31" OR
|
zw_REG_OP = X"D1")) THEN
|
zw_REG_OP = X"D1")) then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ELSIF (rdy_i = '1' and
|
next_state <= s1806;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"A1" OR
|
(zw_REG_OP = X"A1" OR
|
zw_REG_OP = X"41" OR
|
zw_REG_OP = X"41" OR
|
zw_REG_OP = X"01" OR
|
zw_REG_OP = X"01" OR
|
zw_REG_OP = X"21" OR
|
zw_REG_OP = X"21" OR
|
zw_REG_OP = X"C1")) THEN
|
zw_REG_OP = X"C1")) then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s1804;
|
zw_REG_OP = X"B6") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"B6") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
END IF;
|
next_state <= s1802;
|
WHEN s202 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1801;
|
ld_o <= "11";
|
end if;
|
ld_pc_o <= '1';
|
when s1803 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s210 =>
|
|
IF (rdy_i = '1') THEN
|
|
ch_a_o <= d_i;
|
|
ch_b_o <= "0000000" & zw_b2(0);
|
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1810;
|
WHEN s211 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1803;
|
|
end if;
|
|
when s1805 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= "0000000" & zw_b2(0);
|
ch_b_o <= "0000000" & zw_b2(0);
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1809;
|
WHEN s215 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1805;
|
|
end if;
|
|
when s1806 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
END IF;
|
next_state <= s1807;
|
WHEN s217 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1806;
|
ld_o <= "11";
|
end if;
|
ld_pc_o <= '1';
|
when s1802 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s222 =>
|
ld_o <= "11";
|
IF (rdy_i = '1') THEN
|
ld_pc_o <= '1';
|
|
next_state <= s1810;
|
|
else
|
|
next_state <= s1802;
|
|
end if;
|
|
when s1804 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s1808;
|
|
else
|
|
next_state <= s1804;
|
|
end if;
|
|
when s1808 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= zw_b1;
|
ch_a_o <= zw_b1;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
END IF;
|
next_state <= s1803;
|
WHEN s223 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1808;
|
|
end if;
|
|
when s1807 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= "0000000" & zw_b2(0);
|
ch_b_o <= "0000000" & zw_b2(0);
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1809;
|
WHEN s224 =>
|
else
|
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
next_state <= s1807;
|
|
end if;
|
|
when s1810 =>
|
|
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
|
d_regs_in_o <= d_i OR q_a_i;
|
d_regs_in_o <= d_i OR q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i OR q_a_i;
|
ch_a_o <= d_i OR q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
next_state <= FETCH;
|
|
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
|
d_regs_in_o <= d_i XOR q_a_i;
|
d_regs_in_o <= d_i XOR q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i XOR q_a_i;
|
ch_a_o <= d_i XOR q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
next_state <= FETCH;
|
|
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
|
d_regs_in_o <= d_i AND q_a_i;
|
d_regs_in_o <= d_i AND q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i AND q_a_i;
|
ch_a_o <= d_i AND q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
next_state <= FETCH;
|
|
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
|
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
|
zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1;
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1') THEN
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1') then
|
d_regs_in_o <= d_i;
|
d_regs_in_o <= d_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s225 =>
|
else
|
IF ((rdy_i = '1' AND
|
next_state <= s1810;
|
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
end if;
|
|
when s1809 =>
|
|
if ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
|
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
|
d_regs_in_o <= d_i OR q_a_i;
|
d_regs_in_o <= d_i OR q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i OR q_a_i;
|
ch_a_o <= d_i OR q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1' AND
|
next_state <= FETCH;
|
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
elsif ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
|
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
|
d_regs_in_o <= d_i XOR q_a_i;
|
d_regs_in_o <= d_i XOR q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i XOR q_a_i;
|
ch_a_o <= d_i XOR q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1' AND
|
next_state <= FETCH;
|
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
elsif ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
|
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
|
d_regs_in_o <= d_i AND q_a_i;
|
d_regs_in_o <= d_i AND q_a_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i AND q_a_i;
|
ch_a_o <= d_i AND q_a_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF ((rdy_i = '1' AND
|
next_state <= FETCH;
|
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
elsif ((rdy_i = '1' AND
|
|
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
|
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
|
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
|
zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1;
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' AND
|
next_state <= FETCH;
|
zw_b2(0) = '0') THEN
|
elsif (rdy_i = '1' AND
|
|
zw_b2(0) = '0') then
|
d_regs_in_o <= d_i;
|
d_regs_in_o <= d_i;
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s226 =>
|
elsif (rdy_i = '1') then
|
IF (rdy_i = '1' and
|
next_state <= s1810;
|
|
else
|
|
next_state <= s1809;
|
|
end if;
|
|
when s1401 =>
|
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"C6" OR
|
(zw_REG_OP = X"C6" OR
|
zw_REG_OP = X"E6")) THEN
|
zw_REG_OP = X"E6")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s1406;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"D6" OR
|
(zw_REG_OP = X"D6" OR
|
zw_REG_OP = X"F6")) THEN
|
zw_REG_OP = X"F6")) then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s1402;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"CE" OR
|
(zw_REG_OP = X"CE" OR
|
zw_REG_OP = X"EE")) THEN
|
zw_REG_OP = X"EE")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s1403;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"DE" OR
|
(zw_REG_OP = X"DE" OR
|
zw_REG_OP = X"FE")) THEN
|
zw_REG_OP = X"FE")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
END IF;
|
next_state <= s1404;
|
WHEN s243 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1401;
|
|
end if;
|
|
when s1403 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1406;
|
WHEN s244 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1403;
|
|
end if;
|
|
when s1404 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= "0000000" & zw_b2(0);
|
ch_b_o <= "0000000" & zw_b2(0);
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s1405;
|
WHEN s247 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1404;
|
ld_o <= "11";
|
end if;
|
ld_pc_o <= '1';
|
when s1402 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s343 =>
|
ld_o <= "11";
|
IF (rdy_i = '1') THEN
|
ld_pc_o <= '1';
|
|
next_state <= s1406;
|
|
else
|
|
next_state <= s1402;
|
|
end if;
|
|
when s1405 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s1406;
|
|
else
|
|
next_state <= s1405;
|
|
end if;
|
|
when s1406 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= zw_b4;
|
ch_b_o <= zw_b4;
|
END IF;
|
next_state <= s1407;
|
WHEN s250 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s1406;
|
|
end if;
|
|
when s1407 =>
|
|
if (rdy_i = '1') then
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= zw_b1;
|
sig_D_OUT <= zw_b1;
|
END IF;
|
next_state <= s1408;
|
WHEN s251 =>
|
else
|
|
next_state <= s1407;
|
|
end if;
|
|
when s1408 =>
|
ch_a_o <= zw_b1;
|
ch_a_o <= zw_b1;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
WHEN s351 =>
|
next_state <= FETCH;
|
IF (rdy_i = '1' and
|
when s0801 =>
|
zw_REG_OP = X"24") THEN
|
if (rdy_i = '1' and
|
ld_o <= "11";
|
zw_REG_OP = X"24") then
|
ld_pc_o <= '1';
|
ld_o <= "11";
|
ELSIF (rdy_i = '1' and
|
ld_pc_o <= '1';
|
zw_REG_OP = X"2C") THEN
|
next_state <= s0803;
|
ld_o <= "11";
|
elsif (rdy_i = '1' and
|
ld_pc_o <= '1';
|
zw_REG_OP = X"2C") then
|
END IF;
|
ld_o <= "11";
|
WHEN s361 =>
|
ld_pc_o <= '1';
|
IF (rdy_i = '1') THEN
|
next_state <= s0802;
|
|
else
|
|
next_state <= s0801;
|
|
end if;
|
|
when s0803 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= q_a_i AND d_i;
|
ch_a_o <= q_a_i AND d_i;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN s360 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0803;
|
|
end if;
|
|
when s0802 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s0803;
|
WHEN s403 =>
|
else
|
IF (rdy_i = '1' and
|
next_state <= s0802;
|
|
end if;
|
|
when s0601 =>
|
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"1E" or
|
(zw_REG_OP = X"1E" or
|
zw_REG_OP = X"7E" or
|
zw_REG_OP = X"7E" or
|
zw_REG_OP = X"3E" or
|
zw_REG_OP = X"3E" or
|
zw_REG_OP = X"5E")) THEN
|
zw_REG_OP = X"5E")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s0604;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"06" or
|
(zw_REG_OP = X"06" or
|
zw_REG_OP = X"66" or
|
zw_REG_OP = X"66" or
|
zw_REG_OP = X"26" or
|
zw_REG_OP = X"26" or
|
zw_REG_OP = X"46")) THEN
|
zw_REG_OP = X"46")) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s0606;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"16" or
|
(zw_REG_OP = X"16" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"56")) THEN
|
zw_REG_OP = X"56")) then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s0602;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"0E" or
|
(zw_REG_OP = X"0E" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"4E")) THEN
|
zw_REG_OP = X"4E")) then
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
|
END IF;
|
|
WHEN s406 =>
|
|
IF (rdy_i = '1') THEN
|
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s0603;
|
WHEN s407 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0601;
|
|
end if;
|
|
when s0603 =>
|
|
if (rdy_i = '1') then
|
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
|
next_state <= s0606;
|
|
else
|
|
next_state <= s0603;
|
|
end if;
|
|
when s0604 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= "0000000" & zw_b2(0);
|
ch_b_o <= "0000000" & zw_b2(0);
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s0605;
|
WHEN s409 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0604;
|
ld_o <= "11";
|
end if;
|
ld_pc_o <= '1';
|
when s0602 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s416 =>
|
ld_o <= "11";
|
IF (rdy_i = '1' and
|
ld_pc_o <= '1';
|
|
next_state <= s0606;
|
|
else
|
|
next_state <= s0602;
|
|
end if;
|
|
when s0605 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s0606;
|
|
else
|
|
next_state <= s0605;
|
|
end if;
|
|
when s0606 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s0607;
|
|
else
|
|
next_state <= s0606;
|
|
end if;
|
|
when s0607 =>
|
|
if (rdy_i = '1' and
|
(zw_REG_OP = X"06" or
|
(zw_REG_OP = X"06" or
|
zw_REG_OP = X"16" or
|
zw_REG_OP = X"16" or
|
zw_REG_OP = X"0E" or
|
zw_REG_OP = X"0E" or
|
zw_REG_OP = X"1E")) THEN
|
zw_REG_OP = X"1E")) then
|
sig_D_OUT <= d_i(6 downto 0) & '0';
|
sig_D_OUT <= d_i(6 downto 0) & '0';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s0608;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"46" or
|
(zw_REG_OP = X"46" or
|
zw_REG_OP = X"56" or
|
zw_REG_OP = X"56" or
|
zw_REG_OP = X"4E" or
|
zw_REG_OP = X"4E" or
|
zw_REG_OP = X"5E")) THEN
|
zw_REG_OP = X"5E")) then
|
sig_D_OUT <= '0' & d_i(7 downto 1);
|
sig_D_OUT <= '0' & d_i(7 downto 1);
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s0608;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"26" or
|
(zw_REG_OP = X"26" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"36" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"2E" or
|
zw_REG_OP = X"3E")) THEN
|
zw_REG_OP = X"3E")) then
|
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
|
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s0608;
|
|
elsif (rdy_i = '1' and
|
(zw_REG_OP = X"66" or
|
(zw_REG_OP = X"66" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"76" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"6E" or
|
zw_REG_OP = X"7E")) THEN
|
zw_REG_OP = X"7E")) then
|
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
|
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
END IF;
|
next_state <= s0608;
|
WHEN s418 =>
|
else
|
|
next_state <= s0607;
|
|
end if;
|
|
when s0608 =>
|
ch_a_o <= zw_b1;
|
ch_a_o <= zw_b1;
|
ch_b_o <= X"00";
|
ch_b_o <= X"00";
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
WHEN s510 =>
|
next_state <= FETCH;
|
IF (rdy_i = '1' and
|
when s0501 =>
|
zw_REG_OP = X"65") THEN
|
if (rdy_i = '1' and
|
|
zw_REG_OP = X"65") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s0510;
|
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"69" and
|
zw_REG_OP = X"69" and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
|
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
zw_REG_OP = X"75") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"75") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s0502;
|
zw_REG_OP = X"6D") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"6D") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s0503;
|
zw_REG_OP = X"7D") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"7D") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s0505;
|
zw_REG_OP = X"79") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"79") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s0505;
|
zw_REG_OP = X"71") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"71") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ELSIF (rdy_i = '1' and
|
next_state <= s0506;
|
zw_REG_OP = X"61") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"61") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s0504;
|
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"69" and
|
zw_REG_OP = X"69" and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu3(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
|
|
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
|
|
|
|
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
|
zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) +
|
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
|
unsigned (zw_alu(8 downto 5));
|
|
|
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
|
zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) +
|
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
|
unsigned (zw_alu(3 downto 0));
|
|
|
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
|
zw_alu2(3 downto 0) <= '0' &
|
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
|
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
|
sig_SYNC <= '1';
|
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
|
END IF;
|
zw_alu1(4);
|
WHEN s553 =>
|
|
IF (rdy_i = '1') THEN
|
zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR
|
ld_o <= "11";
|
(NOT(zw_alu1(4)) AND zw_alu(8)) OR
|
ld_pc_o <= '1';
|
(zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5));
|
END IF;
|
|
WHEN s555 =>
|
zw_alu2(6) <= zw_alu(9) OR
|
IF (rdy_i = '1') THEN
|
(zw_alu(8) AND zw_alu(7)) OR
|
|
(zw_alu(8) AND zw_alu(6));
|
|
|
|
zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5));
|
|
|
|
zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0';
|
|
zw_alu1(4) <= zw_alu(4) OR
|
|
(zw_alu(3) AND zw_alu(2)) OR
|
|
(zw_alu(3) AND zw_alu(1));
|
|
|
|
zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4));
|
|
zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) +
|
|
reg_F(0);
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s0501;
|
|
end if;
|
|
when s0503 =>
|
|
if (rdy_i = '1') then
|
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
|
next_state <= s0510;
|
|
else
|
|
next_state <= s0503;
|
|
end if;
|
|
when s0505 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s0509;
|
WHEN s558 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0505;
|
|
end if;
|
|
when s0506 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
END IF;
|
next_state <= s0508;
|
WHEN s560 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s0506;
|
ld_o <= "11";
|
end if;
|
ld_pc_o <= '1';
|
when s0502 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s563 =>
|
ld_o <= "11";
|
IF (rdy_i = '1') THEN
|
ld_pc_o <= '1';
|
|
next_state <= s0510;
|
|
else
|
|
next_state <= s0502;
|
|
end if;
|
|
when s0504 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s0507;
|
|
else
|
|
next_state <= s0504;
|
|
end if;
|
|
when s0507 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= zw_b1;
|
ch_a_o <= zw_b1;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
END IF;
|
next_state <= s0503;
|
WHEN s564 =>
|
else
|
IF (rdy_i = '1' AND
|
next_state <= s0507;
|
|
end if;
|
|
when s0509 =>
|
|
if (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
|
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' AND
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu3(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
|
|
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
|
|
|
|
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
|
zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) +
|
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
|
unsigned (zw_alu(8 downto 5));
|
|
|
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
|
zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) +
|
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
|
unsigned (zw_alu(3 downto 0));
|
|
|
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
|
zw_alu2(3 downto 0) <= '0' &
|
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
|
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
|
sig_SYNC <= '1';
|
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
|
END IF;
|
zw_alu1(4);
|
WHEN s565 =>
|
|
IF (rdy_i = '1' and
|
zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR
|
reg_F(3) = '0') THEN
|
(NOT(zw_alu1(4)) AND zw_alu(8)) OR
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
(zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5));
|
|
|
|
zw_alu2(6) <= zw_alu(9) OR
|
|
(zw_alu(8) AND zw_alu(7)) OR
|
|
(zw_alu(8) AND zw_alu(6));
|
|
|
|
zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5));
|
|
|
|
zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0';
|
|
zw_alu1(4) <= zw_alu(4) OR
|
|
(zw_alu(3) AND zw_alu(2)) OR
|
|
(zw_alu(3) AND zw_alu(1));
|
|
|
|
zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4));
|
|
zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) +
|
|
reg_F(0);
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1') then
|
|
next_state <= s0510;
|
|
else
|
|
next_state <= s0509;
|
|
end if;
|
|
when s0510 =>
|
|
if (rdy_i = '1' and
|
|
reg_F(3) = '0') then
|
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
|
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
reg_F(3) = '1') THEN
|
elsif (rdy_i = '1' and
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
reg_F(3) = '1') then
|
|
d_regs_in_o <= zw_alu3(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
|
|
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
|
|
|
|
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
|
zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) +
|
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
|
unsigned (zw_alu(8 downto 5));
|
|
|
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
|
zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) +
|
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
|
unsigned (zw_alu(3 downto 0));
|
|
|
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
|
zw_alu2(3 downto 0) <= '0' &
|
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
|
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
|
sig_SYNC <= '1';
|
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
|
END IF;
|
zw_alu1(4);
|
WHEN s566 =>
|
|
IF (rdy_i = '1') THEN
|
zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR
|
|
(NOT(zw_alu1(4)) AND zw_alu(8)) OR
|
|
(zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5));
|
|
|
|
zw_alu2(6) <= zw_alu(9) OR
|
|
(zw_alu(8) AND zw_alu(7)) OR
|
|
(zw_alu(8) AND zw_alu(6));
|
|
|
|
zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5));
|
|
|
|
zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0';
|
|
zw_alu1(4) <= zw_alu(4) OR
|
|
(zw_alu(3) AND zw_alu(2)) OR
|
|
(zw_alu(3) AND zw_alu(1));
|
|
|
|
zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4));
|
|
zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) +
|
|
reg_F(0);
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s0510;
|
|
end if;
|
|
when s0508 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s0509;
|
WHEN s266 =>
|
else
|
IF (rdy_i = '1' and (
|
next_state <= s0508;
|
|
end if;
|
|
when s0701 =>
|
|
if (rdy_i = '1' and (
|
(reg_F(0) = '1' and zw_REG_OP = X"90") or
|
(reg_F(0) = '1' and zw_REG_OP = X"90") or
|
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
|
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
|
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
|
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
|
(reg_F(7) = '0' and zw_REG_OP = X"30") or
|
(reg_F(7) = '0' and zw_REG_OP = X"30") or
|
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
|
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
|
(reg_F(7) = '1' and zw_REG_OP = X"10") or
|
(reg_F(7) = '1' and zw_REG_OP = X"10") or
|
(reg_F(6) = '1' and zw_REG_OP = X"50") or
|
(reg_F(6) = '1' and zw_REG_OP = X"50") or
|
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
|
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1') THEN
|
next_state <= FETCH;
|
ld_o <= "11";
|
elsif (rdy_i = '1') then
|
ld_pc_o <= '1';
|
|
END IF;
|
|
WHEN s301 =>
|
|
IF (rdy_i = '1' and
|
|
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
|
|
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
|
|
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
|
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_SYNC <= '1';
|
next_state <= s0702;
|
ELSIF (rdy_i = '1') THEN
|
else
|
|
next_state <= s0701;
|
|
end if;
|
|
when s0702 =>
|
|
if (rdy_i = '1' and
|
|
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
|
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
|
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
|
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
|
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
|
WHEN s302 =>
|
|
IF (rdy_i = '1') THEN
|
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN RES =>
|
elsif (rdy_i = '1') then
|
sig_RWn <= '1';
|
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7)
|
sig_RD <= '1';
|
& zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7)
|
ld_o <= "11";
|
& zw_b2(6 downto 0));
|
ld_pc_o <= '1';
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
ld_sp_o <= '1';
|
next_state <= s0703;
|
sig_RWn <= '1';
|
else
|
sig_RD <= '1';
|
next_state <= s0702;
|
WHEN s511 =>
|
end if;
|
IF (rdy_i = '1' and
|
when s0703 =>
|
zw_REG_OP = X"E5") THEN
|
if (rdy_i = '1') then
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s0703;
|
|
end if;
|
|
when s2501 =>
|
|
if (rdy_i = '1' and
|
|
zw_REG_OP = X"E5") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s2510;
|
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"E9" and
|
zw_REG_OP = X"E9" and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
|
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
zw_REG_OP = X"F5") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"F5") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2502;
|
zw_REG_OP = X"ED") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"ED") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= s2503;
|
zw_REG_OP = X"FD") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"FD") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2505;
|
zw_REG_OP = X"F9") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"F9") then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2505;
|
zw_REG_OP = X"F1") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"F1") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ELSIF (rdy_i = '1' and
|
next_state <= s2506;
|
zw_REG_OP = X"E1") THEN
|
elsif (rdy_i = '1' and
|
|
zw_REG_OP = X"E1") then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_x_i;
|
ch_b_o <= q_x_i;
|
ELSIF (rdy_i = '1' and
|
next_state <= s2504;
|
|
elsif (rdy_i = '1' and
|
zw_REG_OP = X"E9" and
|
zw_REG_OP = X"E9" and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
|
|
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
|
|
|
|
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
|
zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) -
|
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
|
unsigned (zw_alu3(7 downto 4));
|
|
zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) -
|
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
|
unsigned (zw_alu3(3 downto 0));
|
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
|
|
|
zw_ALU3(7 downto 0) <= '0' &
|
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
|
(NOT zw_alu2(4)) &
|
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
|
(NOT zw_alu2(4)) &
|
sig_SYNC <= '1';
|
'0' &
|
END IF;
|
'0' &
|
WHEN s559 =>
|
(NOT zw_alu1(4)) &
|
IF (rdy_i = '1') THEN
|
(NOT zw_alu1(4)) &
|
ld_o <= "11";
|
'0';
|
ld_pc_o <= '1';
|
|
END IF;
|
|
WHEN s562 =>
|
zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR
|
IF (rdy_i = '1') THEN
|
(NOT(zw_alu1(4)) AND zw_alu2(3)) OR
|
|
(zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0));
|
|
|
|
zw_alu2(6) <= (zw_alu2(3));
|
|
|
|
zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) +
|
|
zw_alu1(4);
|
|
zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) +
|
|
reg_F(0);
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s2501;
|
|
end if;
|
|
when s2503 =>
|
|
if (rdy_i = '1') then
|
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
|
next_state <= s2510;
|
|
else
|
|
next_state <= s2503;
|
|
end if;
|
|
when s2505 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2509;
|
WHEN s567 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2505;
|
ch_a_o <= d_i;
|
end if;
|
ch_b_o <= X"01";
|
when s2506 =>
|
ld_o <= "11";
|
if (rdy_i = '1') then
|
ld_pc_o <= '1';
|
|
END IF;
|
|
WHEN s568 =>
|
|
IF (rdy_i = '1') THEN
|
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= q_y_i;
|
ch_b_o <= q_y_i;
|
END IF;
|
next_state <= s2507;
|
WHEN s569 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2506;
|
ld_o <= "11";
|
end if;
|
ld_pc_o <= '1';
|
when s2502 =>
|
END IF;
|
if (rdy_i = '1') then
|
WHEN s571 =>
|
ld_o <= "11";
|
IF (rdy_i = '1') THEN
|
ld_pc_o <= '1';
|
|
next_state <= s2510;
|
|
else
|
|
next_state <= s2502;
|
|
end if;
|
|
when s2504 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2508;
|
|
else
|
|
next_state <= s2504;
|
|
end if;
|
|
when s2507 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= d_i;
|
ch_a_o <= d_i;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
END IF;
|
next_state <= s2509;
|
WHEN s572 =>
|
else
|
IF (rdy_i = '1') THEN
|
next_state <= s2507;
|
|
end if;
|
|
when s2508 =>
|
|
if (rdy_i = '1') then
|
ch_a_o <= zw_b1;
|
ch_a_o <= zw_b1;
|
ch_b_o <= X"01";
|
ch_b_o <= X"01";
|
END IF;
|
next_state <= s2503;
|
WHEN s573 =>
|
else
|
IF (rdy_i = '1' AND
|
next_state <= s2508;
|
|
end if;
|
|
when s2509 =>
|
|
if (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '0') THEN
|
reg_F(3) = '0') then
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
|
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' AND
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1' AND
|
zw_b2(0) = '0' and
|
zw_b2(0) = '0' and
|
reg_F(3) = '1') THEN
|
reg_F(3) = '1') then
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
|
|
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
|
|
|
|
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
|
|
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
|
|
|
|
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
|
|
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
|
|
|
|
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
|
zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) -
|
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
|
unsigned (zw_alu3(7 downto 4));
|
sig_SYNC <= '1';
|
zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) -
|
END IF;
|
unsigned (zw_alu3(3 downto 0));
|
WHEN s574 =>
|
|
IF (rdy_i = '1' and
|
zw_ALU3(7 downto 0) <= '0' &
|
reg_F(3) = '0') THEN
|
(NOT zw_alu2(4)) &
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
(NOT zw_alu2(4)) &
|
|
'0' &
|
|
'0' &
|
|
(NOT zw_alu1(4)) &
|
|
(NOT zw_alu1(4)) &
|
|
'0';
|
|
|
|
|
|
zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR
|
|
(NOT(zw_alu1(4)) AND zw_alu2(3)) OR
|
|
(zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0));
|
|
|
|
zw_alu2(6) <= (zw_alu2(3));
|
|
|
|
zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) +
|
|
zw_alu1(4);
|
|
zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) +
|
|
reg_F(0);
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
elsif (rdy_i = '1') then
|
|
next_state <= s2510;
|
|
else
|
|
next_state <= s2509;
|
|
end if;
|
|
when s2510 =>
|
|
if (rdy_i = '1' and
|
|
reg_F(3) = '0') then
|
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
|
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
ELSIF (rdy_i = '1' and
|
next_state <= FETCH;
|
reg_F(3) = '1') THEN
|
elsif (rdy_i = '1' and
|
d_regs_in_o <= zw_ALU(7 downto 0);
|
reg_F(3) = '1') then
|
|
d_regs_in_o <= zw_alu(7 downto 0);
|
load_regs_o <= '1';
|
load_regs_o <= '1';
|
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
|
|
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
|
|
|
|
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
|
|
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
|
|
|
|
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
|
|
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
|
|
|
|
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
|
zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) -
|
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
|
unsigned (zw_alu3(7 downto 4));
|
sig_SYNC <= '1';
|
zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) -
|
END IF;
|
unsigned (zw_alu3(3 downto 0));
|
WHEN s548 =>
|
|
IF (rdy_i = '1') THEN
|
zw_ALU3(7 downto 0) <= '0' &
|
|
(NOT zw_alu2(4)) &
|
|
(NOT zw_alu2(4)) &
|
|
'0' &
|
|
'0' &
|
|
(NOT zw_alu1(4)) &
|
|
(NOT zw_alu1(4)) &
|
|
'0';
|
|
|
|
|
|
zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR
|
|
(NOT(zw_alu1(4)) AND zw_alu2(3)) OR
|
|
(zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0));
|
|
|
|
zw_alu2(6) <= (zw_alu2(3));
|
|
|
|
zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) +
|
|
zw_alu1(4);
|
|
zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) +
|
|
reg_F(0);
|
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s2510;
|
|
end if;
|
|
when s2701 =>
|
|
if (rdy_i = '1') then
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= adr_pc_i (15 downto 8);
|
sig_D_OUT <= adr_pc_i (15 downto 8);
|
END IF;
|
next_state <= s2702;
|
WHEN s551 =>
|
else
|
|
next_state <= s2701;
|
|
end if;
|
|
when s2702 =>
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= adr_pc_i (7 downto 0);
|
sig_D_OUT <= adr_pc_i (7 downto 0);
|
WHEN s552 =>
|
next_state <= s2703;
|
|
when s2703 =>
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_sp_o <= '1';
|
ld_sp_o <= '1';
|
sig_RWn <= '0';
|
sig_RWn <= '0';
|
sig_RD <= '0';
|
sig_RD <= '0';
|
sig_WR <= '1';
|
sig_WR <= '1';
|
sig_D_OUT <= reg_F;
|
sig_D_OUT <= (reg_F AND X"EF");
|
WHEN s576 =>
|
next_state <= s2704;
|
IF (NMI_i = '1') THEN
|
when s2704 =>
|
|
if (nmi_i = '1') then
|
|
next_state <= s2706;
|
|
else
|
|
next_state <= s2705;
|
|
end if;
|
|
when s2707 =>
|
|
if (rdy_i = '1') then
|
|
adr_o <= d_i & zw_b1;
|
rst_nmi_o <= '1';
|
rst_nmi_o <= '1';
|
END IF;
|
ld_o <= "11";
|
WHEN s577 =>
|
ld_pc_o <= '1';
|
IF (rdy_i = '1') THEN
|
sig_SYNC <= '1';
|
|
next_state <= FETCH;
|
|
else
|
|
next_state <= s2707;
|
|
end if;
|
|
when s2706 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2707;
|
|
else
|
|
next_state <= s2706;
|
|
end if;
|
|
when s2705 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s2707;
|
|
else
|
|
next_state <= s2705;
|
|
end if;
|
|
when s0905 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s0907;
|
|
else
|
|
next_state <= s0905;
|
|
end if;
|
|
when s0907 =>
|
|
if (rdy_i = '1') then
|
adr_o <= d_i & zw_b1;
|
adr_o <= d_i & zw_b1;
|
ld_o <= "11";
|
ld_o <= "11";
|
ld_pc_o <= '1';
|
ld_pc_o <= '1';
|
sig_SYNC <= '1';
|
sig_SYNC <= '1';
|
END IF;
|
next_state <= FETCH;
|
WHEN OTHERS =>
|
else
|
NULL;
|
next_state <= s0907;
|
END CASE;
|
end if;
|
END PROCESS output_proc;
|
when s0906 =>
|
|
if (rdy_i = '1') then
|
|
next_state <= s0907;
|
|
else
|
|
next_state <= s0906;
|
|
end if;
|
|
when s0904 =>
|
|
if (nmi_i = '1') then
|
|
rst_nmi_o <= '1';
|
|
next_state <= s0906;
|
|
else
|
|
next_state <= s0905;
|
|
end if;
|
|
when RES =>
|
|
sig_RWn <= '1';
|
|
sig_RD <= '1';
|
|
sig_SYNC <= '1';
|
|
next_state <= RES7;
|
|
when RES7 =>
|
|
ld_o <= "11";
|
|
ld_pc_o <= '1';
|
|
ld_sp_o <= '1';
|
|
sig_RWn <= '1';
|
|
sig_RD <= '1';
|
|
next_state <= s9901;
|
|
when others =>
|
|
next_state <= RES;
|
|
end case;
|
|
end process nextstate_proc;
|
|
|
-- Concurrent Statements
|
-- Concurrent Statements
|
-- Clocked output assignments
|
-- Clocked output assignments
|
d_o <= d_o_cld;
|
d_o <= d_o_cld;
|
rd_o <= rd_o_cld;
|
rd_o <= rd_o_cld;
|
sync_o <= sync_o_cld;
|
sync_o <= sync_o_cld;
|
wr_n_o <= wr_n_o_cld;
|
wr_n_o <= wr_n_o_cld;
|
wr_o <= wr_o_cld;
|
wr_o <= wr_o_cld;
|
END fsm;
|
end fsm;
|
|
|
No newline at end of file
|
No newline at end of file
|
