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-- VHDL Entity R6502_TC.R6502_TC.symbol
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-- VHDL Entity r6502_tc.r6502_tc.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 14:13:53 08.03.2010
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-- at - 10:34:09 11.09.2018
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY R6502_TC IS
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entity r6502_tc is
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PORT(
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port(
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clk_clk_i : IN std_logic;
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clk_clk_i : in std_logic;
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d_i : IN std_logic_vector (7 DOWNTO 0);
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d_i : in std_logic_vector (7 downto 0);
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irq_n_i : IN std_logic;
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irq_n_i : in std_logic;
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nmi_n_i : IN std_logic;
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nmi_n_i : in std_logic;
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rdy_i : IN std_logic;
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rdy_i : in std_logic;
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rst_rst_n_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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so_n_i : IN std_logic;
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so_n_i : in std_logic;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
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a_o : out std_logic_vector (15 downto 0);
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d_o : OUT std_logic_vector (7 DOWNTO 0);
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d_o : out std_logic_vector (7 downto 0);
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rd_o : OUT std_logic;
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rd_o : out std_logic;
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sync_o : OUT std_logic;
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sync_o : out std_logic;
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wr_n_o : OUT std_logic;
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wr_n_o : out std_logic;
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wr_o : OUT std_logic
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wr_o : out std_logic
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);
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);
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-- Declarations
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-- Declarations
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END R6502_TC ;
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end r6502_tc ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- scantara2003@yahoo.de
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-- (email: opencores@vivare-services.com)
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- Versions:
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- Revision 1.4 2018/09/15 22:07:00 jens
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-- - RESET generates SYNC now, 1 dead cycle
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-- delayed
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-- - ADC / SBC flags and A like R6502 now
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-- - Bug Fix ADC and SBC in decimal mode
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-- (all op codes - "Overflow" flag was computed
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-- wrong)
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-- - Interrupt priority order is now: BRK - NMI -
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-- IRQ
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-- - Performance improvements on-going
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-- (Mealy -> Moore)
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-- - Bug Fixes All Branch Instructions
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-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC,
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-- BVS)
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-- 3 cycles now if branch forward occur and
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-- the branch instruction lies on a xxFEh
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-- location.
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-- - Bug Fix Hardware Interrupts NMI & IRQ -
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-- "SYNC" now
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--
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-- Revision 1.4 BETA 2013/07/24 11:11:00 jens
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-- - Changing the title block and internal revision history
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-- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong)
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--
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-- Revision 1.3 2009/01/04 10:20:50 eda
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-- Changes for cosmetic issues only
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--
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-- Revision 1.2 2009/01/04 09:23:12 eda
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-- - Delete unused nets and blocks
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-- - Rename blocks
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-- - Re-arrage FSM symbols in block FSM_Execution_Unit
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- Revision 1.1 2009/01/03 16:36:48 eda
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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-- Production version
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--
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- CVS Revisins History
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--
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--
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-- $Log: struct.bd,v $
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-- <<-- more -->>
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-- Title: Top Level
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-- Path: R6502_TC/R6502_TC/struct
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-- Edited: by eda on 08 Feb 2010
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--
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--
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-- VHDL Architecture R6502_TC.R6502_TC.struct
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-- VHDL Architecture r6502_tc.r6502_tc.struct
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 14:13:53 08.03.2010
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-- at - 22:34:11 15.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
|
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--
|
|
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
|
--
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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LIBRARY R6502_TC;
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library r6502_tc;
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ARCHITECTURE struct OF R6502_TC IS
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architecture struct of r6502_tc is
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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|
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-- Component Declarations
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-- Component Declarations
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COMPONENT Core
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component core
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PORT (
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port (
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clk_clk_i : IN std_logic ;
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clk_clk_i : in std_logic ;
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d_i : IN std_logic_vector (7 DOWNTO 0);
|
d_i : in std_logic_vector (7 downto 0);
|
irq_n_i : IN std_logic ;
|
irq_n_i : in std_logic ;
|
nmi_n_i : IN std_logic ;
|
nmi_n_i : in std_logic ;
|
rdy_i : IN std_logic ;
|
rdy_i : in std_logic ;
|
rst_rst_n_i : IN std_logic ;
|
rst_rst_n_i : in std_logic ;
|
so_n_i : IN std_logic ;
|
so_n_i : in std_logic ;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
|
a_o : out std_logic_vector (15 downto 0);
|
d_o : OUT std_logic_vector (7 DOWNTO 0);
|
d_o : out std_logic_vector (7 downto 0);
|
rd_o : OUT std_logic ;
|
rd_o : out std_logic ;
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sync_o : OUT std_logic ;
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sync_o : out std_logic ;
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wr_n_o : OUT std_logic ;
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wr_n_o : out std_logic ;
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wr_o : OUT std_logic
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wr_o : out std_logic
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);
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);
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END COMPONENT;
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end component;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : Core USE ENTITY R6502_TC.Core;
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for all : core use entity r6502_tc.core;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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begin
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|
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-- Instance port mappings.
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-- Instance port mappings.
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U_0 : Core
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U_0 : core
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PORT MAP (
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port map (
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clk_clk_i => clk_clk_i,
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clk_clk_i => clk_clk_i,
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d_i => d_i,
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d_i => d_i,
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irq_n_i => irq_n_i,
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irq_n_i => irq_n_i,
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nmi_n_i => nmi_n_i,
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nmi_n_i => nmi_n_i,
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rdy_i => rdy_i,
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rdy_i => rdy_i,
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| Line 114... |
Line 144... |
sync_o => sync_o,
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sync_o => sync_o,
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wr_n_o => wr_n_o,
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wr_n_o => wr_n_o,
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wr_o => wr_o
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wr_o => wr_o
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);
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);
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|
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END struct;
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end struct;
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No newline at end of file
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No newline at end of file
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