Line 1... |
Line 1... |
-- VHDL Entity R6502_TC.Reg_PC.symbol
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-- VHDL Entity r6502_tc.reg_pc.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 18:39:48 08.02.2010
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-- at - 11:45:07 11.09.2018
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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ENTITY Reg_PC IS
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entity reg_pc is
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PORT(
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port(
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adr_i : IN std_logic_vector (15 DOWNTO 0);
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : IN std_logic;
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clk_clk_i : in std_logic;
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ld_i : IN std_logic_vector (1 DOWNTO 0);
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ld_i : in std_logic_vector (1 downto 0);
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ld_pc_i : IN std_logic;
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ld_pc_i : in std_logic;
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offset_i : IN std_logic_vector (15 DOWNTO 0);
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offset_i : in std_logic_vector (15 downto 0);
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rst_rst_n_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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sel_pc_in_i : IN std_logic;
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sel_pc_in_i : in std_logic;
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sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
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sel_pc_val_i : in std_logic_vector (1 downto 0);
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adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
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adr_nxt_pc_o : out std_logic_vector (15 downto 0);
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adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
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adr_pc_o : out std_logic_vector (15 downto 0)
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);
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);
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-- Declarations
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-- Declarations
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|
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END Reg_PC ;
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end reg_pc ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- scantara2003@yahoo.de
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-- (email: opencores@vivare-services.com)
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- Versions:
|
-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- Revision 1.15 2013/07/21 11:11:00 jens
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|
-- - Change mux 3-1 to mux 4-1 for vendors like Xilinx
|
|
-- - Changing the title block and internal revision history
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- Revision 1.3 2009/01/04 10:20:50 eda
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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-- Changes for cosmetic issues only
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--
|
--
|
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
|
-- Revision 1.2 2009/01/04 09:23:12 eda
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-- - Delete unused nets and blocks
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-- - Rename blocks
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-- - Re-arrage FSM symbols in block FSM_Execution_Unit
|
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--
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|
-- Revision 1.1 2009/01/03 16:36:48 eda
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-- Production Release
|
--
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--
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-- CVS Revisins History
|
|
--
|
--
|
-- $Log: struct.bd,v $
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|
-- <<-- more -->>
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-- Title: Program Counter Logic
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-- Path: R6502_TC/Reg_PC/struct
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-- Edited: by eda on 08 Feb 2010
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--
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--
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-- VHDL Architecture R6502_TC.Reg_PC.struct
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-- VHDL Architecture r6502_tc.reg_pc.struct
|
--
|
--
|
-- Created:
|
-- Created:
|
-- by - eda.UNKNOWN (ENTW1)
|
-- by - eda.UNKNOWN (ENTW-7HPZ200)
|
-- at - 18:39:49 08.02.2010
|
-- at - 11:45:07 11.09.2018
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
|
|
--
|
|
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
|
|
--
|
|
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
|
--
|
--
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
|
|
--
|
--
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_arith.all;
|
USE ieee.std_logic_arith.all;
|
|
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|
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ARCHITECTURE struct OF Reg_PC IS
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architecture struct of reg_pc is
|
|
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-- Architecture declarations
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-- Architecture declarations
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|
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-- Internal signal declarations
|
-- Internal signal declarations
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SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0);
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signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
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SIGNAL adr_pc_low_o_i : std_logic_vector(7 DOWNTO 0);
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signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
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SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
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signal adr_pc_o_i : std_logic_vector(15 downto 0);
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SIGNAL ci_o_i : std_logic;
|
signal ci_o_i : std_logic;
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SIGNAL cout_pc_o_i : std_logic;
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signal cout_pc_o_i : std_logic;
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SIGNAL load3_o_i : std_logic;
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signal load3_o_i : std_logic;
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SIGNAL load_o_i : std_logic;
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signal load_o_i : std_logic;
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SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0);
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signal offset_high_o_i : std_logic_vector(7 downto 0);
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SIGNAL offset_low_o_i : std_logic_vector(7 DOWNTO 0);
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signal offset_low_o_i : std_logic_vector(7 downto 0);
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SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
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signal val_o_i : std_logic_vector(7 downto 0);
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SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
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signal val_one : std_logic_vector(7 downto 0);
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SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
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signal val_zero : std_logic_vector(7 downto 0);
|
|
|
-- Implicit buffer signal declarations
|
-- Implicit buffer signal declarations
|
SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
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signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
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SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
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signal adr_pc_o_internal : std_logic_vector (15 downto 0);
|
|
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
|
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
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SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
|
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
|
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
|
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
|
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'
|
-- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split'
|
SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0);
|
signal mw_U_3temp_din : std_logic_vector(15 downto 0);
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|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'
|
-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split'
|
SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0);
|
signal mw_U_5temp_din : std_logic_vector(15 downto 0);
|
|
|
|
|
BEGIN
|
begin
|
|
|
-- ModuleWare code(v1.9) for instance 'U_2' of 'add'
|
-- ModuleWare code(v1.12) for instance 'U_2' of 'add'
|
u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i)
|
u_2combo_proc: process (adr_pc_low_o_i, val_o_i)
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VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
|
variable temp_din0 : std_logic_vector(8 downto 0);
|
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
|
variable temp_din1 : std_logic_vector(8 downto 0);
|
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
|
variable temp_sum : unsigned(8 downto 0);
|
VARIABLE temp_carry : std_logic;
|
variable temp_carry : std_logic;
|
BEGIN
|
begin
|
temp_din0 := '0' & adr_pc_low_o_i;
|
temp_din0 := '0' & adr_pc_low_o_i;
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temp_din1 := '0' & val_o_i;
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temp_din1 := '0' & val_o_i;
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temp_carry := '0';
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temp_carry := '0';
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temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
|
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
|
cout_pc_o_i <= temp_sum(8) ;
|
cout_pc_o_i <= temp_sum(8) ;
|
END PROCESS u_2combo_proc;
|
end process u_2combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
|
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
|
u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
|
u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
|
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
|
variable temp_din0 : std_logic_vector(8 downto 0);
|
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
|
variable temp_din1 : std_logic_vector(8 downto 0);
|
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
|
variable temp_sum : unsigned(8 downto 0);
|
VARIABLE temp_carry : std_logic;
|
variable temp_carry : std_logic;
|
BEGIN
|
begin
|
temp_din0 := '0' & adr_pc_high_o_i;
|
temp_din0 := '0' & adr_pc_high_o_i;
|
temp_din1 := '0' & offset_high_o_i;
|
temp_din1 := '0' & offset_high_o_i;
|
temp_carry := ci_o_i;
|
temp_carry := ci_o_i;
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
|
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
|
END PROCESS u_11combo_proc;
|
end process u_11combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
|
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
|
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
|
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
|
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
|
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
|
BEGIN
|
begin
|
IF (rst_rst_n_i = '0') THEN
|
if (rst_rst_n_i = '0') then
|
mw_U_0reg_cval <= "00000000";
|
mw_U_0reg_cval <= "00000000";
|
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
|
elsif (clk_clk_i'event and clk_clk_i='1') then
|
IF (load_o_i = '1') THEN
|
if (load_o_i = '1') then
|
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
|
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END PROCESS u_0seq_proc;
|
end process u_0seq_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
|
-- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
|
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
|
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
|
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
|
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
|
BEGIN
|
begin
|
IF (rst_rst_n_i = '0') THEN
|
if (rst_rst_n_i = '0') then
|
mw_U_4reg_cval <= "00000000";
|
mw_U_4reg_cval <= "00000000";
|
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
|
elsif (clk_clk_i'event and clk_clk_i='1') then
|
IF (load3_o_i = '1') THEN
|
if (load3_o_i = '1') then
|
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
|
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END PROCESS u_4seq_proc;
|
end process u_4seq_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
|
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
|
load_o_i <= ld_pc_i AND ld_i(0);
|
load_o_i <= ld_pc_i and ld_i(0);
|
|
|
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
|
-- ModuleWare code(v1.12) for instance 'U_7' of 'and'
|
load3_o_i <= ld_pc_i AND ld_i(1);
|
load3_o_i <= ld_pc_i and ld_i(1);
|
|
|
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
|
-- ModuleWare code(v1.12) for instance 'U_10' of 'and'
|
ci_o_i <= cout_pc_o_i AND ld_pc_i;
|
ci_o_i <= cout_pc_o_i and ld_pc_i;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
|
-- ModuleWare code(v1.12) for instance 'U_1' of 'constval'
|
val_zero <= "00000000";
|
val_zero <= "00000000";
|
|
|
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
|
-- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
|
val_one <= "00000001";
|
val_one <= "00000001";
|
|
|
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
|
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
|
u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
|
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
|
BEGIN
|
begin
|
CASE sel_pc_in_i IS
|
case sel_pc_in_i is
|
WHEN '0' => adr_pc_o_i <= adr_pc_o_internal;
|
when '0' => adr_pc_o_i <= adr_pc_o_internal;
|
WHEN '1' => adr_pc_o_i <= adr_i;
|
when '1' => adr_pc_o_i <= adr_i;
|
WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
|
when others => adr_pc_o_i <= (others => 'X');
|
END CASE;
|
end case;
|
END PROCESS u_8combo_proc;
|
end process u_8combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
|
-- ModuleWare code(v1.12) for instance 'U_13' of 'mux'
|
u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
|
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
|
sel_pc_val_i)
|
sel_pc_val_i)
|
BEGIN
|
begin
|
CASE sel_pc_val_i IS
|
case sel_pc_val_i is
|
WHEN "00" => val_o_i <= val_one;
|
when "00" => val_o_i <= val_one;
|
WHEN "01" => val_o_i <= val_zero;
|
when "01" => val_o_i <= val_zero;
|
WHEN "10" => val_o_i <= offset_low_o_i;
|
when "10" => val_o_i <= offset_low_o_i;
|
WHEN "11" => val_o_i <= val_zero;
|
when "11" => val_o_i <= val_zero;
|
WHEN OTHERS => val_o_i <= (OTHERS => 'X');
|
when others => val_o_i <= (others => 'X');
|
END CASE;
|
end case;
|
END PROCESS u_13combo_proc;
|
end process u_13combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
|
-- ModuleWare code(v1.12) for instance 'U_3' of 'split'
|
mw_U_3temp_din <= adr_pc_o_i;
|
mw_U_3temp_din <= adr_pc_o_i;
|
u_3combo_proc: PROCESS (mw_U_3temp_din)
|
u_3combo_proc: process (mw_U_3temp_din)
|
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
|
variable temp_din: std_logic_vector(15 downto 0);
|
BEGIN
|
begin
|
temp_din := mw_U_3temp_din(15 DOWNTO 0);
|
temp_din := mw_U_3temp_din(15 downto 0);
|
adr_pc_low_o_i <= temp_din(7 DOWNTO 0);
|
adr_pc_low_o_i <= temp_din(7 downto 0);
|
adr_pc_high_o_i <= temp_din(15 DOWNTO 8);
|
adr_pc_high_o_i <= temp_din(15 downto 8);
|
END PROCESS u_3combo_proc;
|
end process u_3combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
|
-- ModuleWare code(v1.12) for instance 'U_5' of 'split'
|
mw_U_5temp_din <= offset_i;
|
mw_U_5temp_din <= offset_i;
|
u_5combo_proc: PROCESS (mw_U_5temp_din)
|
u_5combo_proc: process (mw_U_5temp_din)
|
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
|
variable temp_din: std_logic_vector(15 downto 0);
|
BEGIN
|
begin
|
temp_din := mw_U_5temp_din(15 DOWNTO 0);
|
temp_din := mw_U_5temp_din(15 downto 0);
|
offset_low_o_i <= temp_din(7 DOWNTO 0);
|
offset_low_o_i <= temp_din(7 downto 0);
|
offset_high_o_i <= temp_din(15 DOWNTO 8);
|
offset_high_o_i <= temp_din(15 downto 8);
|
END PROCESS u_5combo_proc;
|
end process u_5combo_proc;
|
|
|
-- Instance port mappings.
|
-- Instance port mappings.
|
|
|
-- Implicit buffered output assignments
|
-- Implicit buffered output assignments
|
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
|
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
|
adr_pc_o <= adr_pc_o_internal;
|
adr_pc_o <= adr_pc_o_internal;
|
|
|
END struct;
|
end struct;
|
|
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No newline at end of file
|
No newline at end of file
|