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-- VHDL Entity R6502_TC.RegBank_AXY.symbol
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-- VHDL Entity r6502_tc.regbank_axy.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 18:39:49 08.02.2010
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-- at - 11:41:39 11.09.2018
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY RegBank_AXY IS
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entity regbank_axy is
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PORT(
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port(
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clk_clk_i : IN std_logic;
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clk_clk_i : in std_logic;
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d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
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d_regs_in_i : in std_logic_vector (7 downto 0);
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load_regs_i : IN std_logic;
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load_regs_i : in std_logic;
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rst_rst_n_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
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sel_rb_in_i : in std_logic_vector (1 downto 0);
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sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
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d_regs_out_o : out std_logic_vector (7 downto 0);
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q_a_o : OUT std_logic_vector (7 DOWNTO 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_x_o : OUT std_logic_vector (7 DOWNTO 0);
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q_x_o : out std_logic_vector (7 downto 0);
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q_y_o : OUT std_logic_vector (7 DOWNTO 0)
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q_y_o : out std_logic_vector (7 downto 0)
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);
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);
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-- Declarations
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-- Declarations
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END RegBank_AXY ;
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end regbank_axy ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- scantara2003@yahoo.de
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-- (email: opencores@vivare-services.com)
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- Versions:
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- Revision 1.5 2013/07/24 11:11:00 jens
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-- - Changing the title block and internal revision history
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-- - Change mux 3-1 to mux 4-1 for vendors like Xilinx
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- Revision 1.3 2009/01/04 10:20:50 eda
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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-- Changes for cosmetic issues only
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--
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- Revision 1.2 2009/01/04 09:23:12 eda
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-- - Delete unused nets and blocks
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-- - Rename blocks
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-- - Re-arrage FSM symbols in block FSM_Execution_Unit
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--
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-- Revision 1.1 2009/01/03 16:36:48 eda
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-- Production Release
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--
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--
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-- CVS Revisins History
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--
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--
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-- $Log: struct.bd,v $
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-- <<-- more -->>
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-- Title: Register Bank for register A, X and Y
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-- Path: R6502_TC/RegBank_AXY/struct
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-- Edited: by eda on 08 Feb 2010
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--
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--
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-- VHDL Architecture R6502_TC.RegBank_AXY.struct
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-- VHDL Architecture r6502_tc.regbank_axy.struct
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTW1)
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 18:39:49 08.02.2010
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-- at - 11:44:39 11.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF RegBank_AXY IS
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architecture struct of regbank_axy is
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL ld : std_logic_vector(2 DOWNTO 0);
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signal ld : std_logic_vector(2 downto 0);
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SIGNAL load1_o_i : std_logic;
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signal load1_o_i : std_logic;
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SIGNAL load2_o_i : std_logic;
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signal load2_o_i : std_logic;
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SIGNAL load_o_i : std_logic;
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signal load_o_i : std_logic;
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SIGNAL q_mux_o_i : std_logic_vector(7 DOWNTO 0);
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signal q_mux_o_i : std_logic_vector(7 downto 0);
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SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
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signal val_zero : std_logic_vector(7 downto 0);
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-- Implicit buffer signal declarations
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-- Implicit buffer signal declarations
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SIGNAL q_a_o_internal : std_logic_vector (7 DOWNTO 0);
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signal q_a_o_internal : std_logic_vector (7 downto 0);
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SIGNAL q_x_o_internal : std_logic_vector (7 DOWNTO 0);
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signal q_x_o_internal : std_logic_vector (7 downto 0);
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SIGNAL q_y_o_internal : std_logic_vector (7 DOWNTO 0);
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signal q_y_o_internal : std_logic_vector (7 downto 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
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-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
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SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
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signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
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-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
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SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
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signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
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-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff'
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SIGNAL mw_U_5reg_cval : std_logic_vector(7 DOWNTO 0);
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signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
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BEGIN
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begin
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
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q_a_o_internal <= mw_U_0reg_cval;
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q_a_o_internal <= mw_U_0reg_cval;
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u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
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BEGIN
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begin
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IF (rst_rst_n_i = '0') THEN
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if (rst_rst_n_i = '0') then
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mw_U_0reg_cval <= "00000000";
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mw_U_0reg_cval <= "00000000";
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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elsif (clk_clk_i'event and clk_clk_i='1') then
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IF (load_o_i = '1') THEN
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if (load_o_i = '1') then
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mw_U_0reg_cval <= q_mux_o_i;
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mw_U_0reg_cval <= q_mux_o_i;
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS u_0seq_proc;
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end process u_0seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
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-- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
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q_x_o_internal <= mw_U_4reg_cval;
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q_x_o_internal <= mw_U_4reg_cval;
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u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
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BEGIN
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begin
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IF (rst_rst_n_i = '0') THEN
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if (rst_rst_n_i = '0') then
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mw_U_4reg_cval <= "00000000";
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mw_U_4reg_cval <= "00000000";
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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elsif (clk_clk_i'event and clk_clk_i='1') then
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IF (load1_o_i = '1') THEN
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if (load1_o_i = '1') then
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mw_U_4reg_cval <= q_mux_o_i;
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mw_U_4reg_cval <= q_mux_o_i;
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS u_4seq_proc;
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end process u_4seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
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-- ModuleWare code(v1.12) for instance 'U_5' of 'adff'
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q_y_o_internal <= mw_U_5reg_cval;
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q_y_o_internal <= mw_U_5reg_cval;
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u_5seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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u_5seq_proc: process (clk_clk_i, rst_rst_n_i)
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BEGIN
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begin
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IF (rst_rst_n_i = '0') THEN
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if (rst_rst_n_i = '0') then
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mw_U_5reg_cval <= "00000000";
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mw_U_5reg_cval <= "00000000";
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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elsif (clk_clk_i'event and clk_clk_i='1') then
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IF (load2_o_i = '1') THEN
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if (load2_o_i = '1') then
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mw_U_5reg_cval <= q_mux_o_i;
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mw_U_5reg_cval <= q_mux_o_i;
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS u_5seq_proc;
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end process u_5seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
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-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
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load_o_i <= load_regs_i AND ld(0);
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load_o_i <= load_regs_i and ld(0);
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-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
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-- ModuleWare code(v1.12) for instance 'U_7' of 'and'
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load1_o_i <= load_regs_i AND ld(1);
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load1_o_i <= load_regs_i and ld(1);
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-- ModuleWare code(v1.9) for instance 'U_8' of 'and'
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-- ModuleWare code(v1.12) for instance 'U_8' of 'and'
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load2_o_i <= load_regs_i AND ld(2);
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load2_o_i <= load_regs_i and ld(2);
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-- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
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-- ModuleWare code(v1.12) for instance 'U_2' of 'constval'
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val_zero <= "00000000";
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val_zero <= "00000000";
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-- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
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-- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1'
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u_1combo_proc: PROCESS (sel_reg_i)
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u_1combo_proc: process (sel_reg_i)
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BEGIN
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begin
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ld <= (OTHERS => '0');
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ld <= (others => '0');
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CASE sel_reg_i IS
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case sel_reg_i is
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WHEN "00" => ld(0) <= '1';
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when "00" => ld(0) <= '1';
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WHEN "01" => ld(1) <= '1';
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when "01" => ld(1) <= '1';
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WHEN "10" => ld(2) <= '1';
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when "10" => ld(2) <= '1';
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WHEN OTHERS => ld <= (OTHERS => '0');
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when others => ld <= (others => '0');
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END CASE;
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end case;
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END PROCESS u_1combo_proc;
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end process u_1combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
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u_2combo_proc: PROCESS(q_a_o_internal, q_x_o_internal, q_y_o_internal,
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val_zero, sel_rb_out_i)
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BEGIN
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CASE sel_rb_out_i IS
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WHEN "00" => d_regs_out_o <= q_a_o_internal;
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WHEN "01" => d_regs_out_o <= q_x_o_internal;
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WHEN "10" => d_regs_out_o <= q_y_o_internal;
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WHEN "11" => d_regs_out_o <= val_zero;
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WHEN OTHERS => d_regs_out_o <= (OTHERS => 'X');
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END CASE;
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END PROCESS u_2combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
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-- ModuleWare code(v1.12) for instance 'U_3' of 'mux'
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u_3combo_proc: PROCESS(q_a_o_internal, q_y_o_internal, q_x_o_internal,
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u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
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d_regs_in_i, sel_rb_in_i)
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d_regs_in_i, sel_rb_in_i)
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BEGIN
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begin
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CASE sel_rb_in_i IS
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case sel_rb_in_i is
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WHEN "00" => q_mux_o_i <= q_a_o_internal;
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when "00" => q_mux_o_i <= q_a_o_internal;
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WHEN "01" => q_mux_o_i <= q_y_o_internal;
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when "01" => q_mux_o_i <= q_y_o_internal;
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WHEN "10" => q_mux_o_i <= q_x_o_internal;
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when "10" => q_mux_o_i <= q_x_o_internal;
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WHEN "11" => q_mux_o_i <= d_regs_in_i;
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when "11" => q_mux_o_i <= d_regs_in_i;
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WHEN OTHERS => q_mux_o_i <= (OTHERS => 'X');
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when others => q_mux_o_i <= (others => 'X');
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END CASE;
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end case;
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END PROCESS u_3combo_proc;
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end process u_3combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_9' of 'mux'
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u_9combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
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val_zero, sel_rb_out_i)
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begin
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case sel_rb_out_i is
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when "00" => d_regs_out_o <= q_a_o_internal;
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when "01" => d_regs_out_o <= q_x_o_internal;
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when "10" => d_regs_out_o <= q_y_o_internal;
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when "11" => d_regs_out_o <= val_zero;
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when others => d_regs_out_o <= (others => 'X');
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end case;
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end process u_9combo_proc;
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-- Instance port mappings.
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-- Instance port mappings.
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-- Implicit buffered output assignments
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-- Implicit buffered output assignments
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q_a_o <= q_a_o_internal;
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q_a_o <= q_a_o_internal;
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q_x_o <= q_x_o_internal;
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q_x_o <= q_x_o_internal;
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q_y_o <= q_y_o_internal;
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q_y_o <= q_y_o_internal;
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END struct;
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end struct;
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No newline at end of file
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No newline at end of file
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