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[/] [cpu65c02_true_cycle/] [trunk/] [TO_DO_list.txt] - Diff between revs 15 and 18
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Rev 18 |
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(July 31th 2013)
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- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"
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- (DONE) Offer a high level testbench in assembler for testing all Op Codes
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Including Klaus Dormann's "65c02_*_test" suite
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- (DONE) Because of translation errors the Verilog sources are no longer
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available
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- (DONE) Create "golden" simulation files for Modelsim/QuestaSim
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- (75%) Finish working for Specification of cpu65C02_tc
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- (85%) Finish working for Specification of cpu65C02_tc
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(February 25th 2009)
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(February 25th 2009)
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- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
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- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
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- (DONE) CORRECTED "RMBx" & "SMBx" (wrong: bit translation)
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- (DONE) CORRECTED "RMBx" & "SMBx" (wrong: bit translation)
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- (DONE) RENAME all states of "FSM Execution Unit" for better reading
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- (DONE) RENAME all states of "FSM Execution Unit" for better reading
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- (85%) Finish working for Specification of cpu65C02_tc
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- (85%) Finish working for Specification of cpu65C02_tc
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- (DONE) CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
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- (DONE) CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles
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instead of 7)
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- (DONE) OPTIMIZE end states of "STA" (s197,s207,s200,s213)
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- (DONE) OPTIMIZE end states of "STA" (s197,s207,s200,s213)
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(January, 4th 2009)
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(January, 4th 2009)
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- (DONE) Remove unused nets, register and modules
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- (DONE) Remove unused nets, register and modules
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- (DONE) Update the HDL Designer files for better viewing and
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- (DONE) Update the HDL Designer files for better viewing and
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