-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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--
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--
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-- This code is free software: you can redistribute it and/or modify
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-- This code is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this code (see the file named COPYING).
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-- along with this code (see the file named COPYING).
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-- If not, see http://www.gnu.org/licenses/.
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-- If not, see http://www.gnu.org/licenses/.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Module Name: alu - Behavioral
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-- Module Name: alu - Behavioral
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-- Create Date: 13:51:24 11/07/2009
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-- Create Date: 13:51:24 11/07/2009
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-- Description: arithmetic logic unit of a CPU
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-- Description: arithmetic logic unit of a CPU
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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|
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use work.common.ALL;
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use work.common.ALL;
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entity alu is
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entity alu is
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port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
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port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
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I_BIT : in std_logic_vector( 3 downto 0);
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I_BIT : in std_logic_vector( 3 downto 0);
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I_D : in std_logic_vector(15 downto 0);
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I_D : in std_logic_vector(15 downto 0);
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I_D0 : in std_logic;
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I_D0 : in std_logic;
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I_DIN : in std_logic_vector( 7 downto 0);
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I_DIN : in std_logic_vector( 7 downto 0);
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I_FLAGS : in std_logic_vector( 7 downto 0);
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I_FLAGS : in std_logic_vector( 7 downto 0);
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I_IMM : in std_logic_vector( 7 downto 0);
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I_IMM : in std_logic_vector( 7 downto 0);
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I_PC : in std_logic_vector(15 downto 0);
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I_PC : in std_logic_vector(15 downto 0);
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I_R : in std_logic_vector(15 downto 0);
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I_R : in std_logic_vector(15 downto 0);
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I_R0 : in std_logic;
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I_R0 : in std_logic;
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I_RSEL : in std_logic_vector( 1 downto 0);
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I_RSEL : in std_logic_vector( 1 downto 0);
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Q_FLAGS : out std_logic_vector( 9 downto 0);
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Q_FLAGS : out std_logic_vector( 9 downto 0);
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Q_DOUT : out std_logic_vector(15 downto 0));
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Q_DOUT : out std_logic_vector(15 downto 0));
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end alu;
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end alu;
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architecture Behavioral of alu is
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architecture Behavioral of alu is
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function ze(A: std_logic_vector(7 downto 0)) return std_logic is
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function ze(A: std_logic_vector(7 downto 0)) return std_logic is
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begin
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begin
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return not (A(0) or A(1) or A(2) or A(3) or
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return not (A(0) or A(1) or A(2) or A(3) or
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A(4) or A(5) or A(6) or A(7));
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A(4) or A(5) or A(6) or A(7));
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end;
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end;
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function cy(D, R, S: std_logic) return std_logic is
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function cy(D, R, S: std_logic) return std_logic is
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begin
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begin
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return (D and R) or (D and not S) or (R and not S);
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return (D and R) or (D and not S) or (R and not S);
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end;
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end;
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function ov(D, R, S: std_logic) return std_logic is
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function ov(D, R, S: std_logic) return std_logic is
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begin
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begin
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return (D and R and (not S)) or ((not D) and (not R) and S);
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return (D and R and (not S)) or ((not D) and (not R) and S);
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end;
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end;
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function si(D, R, S: std_logic) return std_logic is
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function si(D, R, S: std_logic) return std_logic is
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begin
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begin
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return S xor ov(D, R, S);
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return S xor ov(D, R, S);
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end;
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end;
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signal L_ADC_DR : std_logic_vector( 7 downto 0); -- D + R + Carry
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signal L_ADC_DR : std_logic_vector( 7 downto 0); -- D + R + Carry
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signal L_ADD_DR : std_logic_vector( 7 downto 0); -- D + R
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signal L_ADD_DR : std_logic_vector( 7 downto 0); -- D + R
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signal L_ADIW_D : std_logic_vector(15 downto 0); -- D + IMM
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signal L_ADIW_D : std_logic_vector(15 downto 0); -- D + IMM
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signal L_AND_DR : std_logic_vector( 7 downto 0); -- D and R
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signal L_AND_DR : std_logic_vector( 7 downto 0); -- D and R
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signal L_ASR_D : std_logic_vector( 7 downto 0); -- (signed D) >> 1
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signal L_ASR_D : std_logic_vector( 7 downto 0); -- (signed D) >> 1
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signal L_D8 : std_logic_vector( 7 downto 0); -- D(7 downto 0)
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signal L_D8 : std_logic_vector( 7 downto 0); -- D(7 downto 0)
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signal L_DEC_D : std_logic_vector( 7 downto 0); -- D - 1
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signal L_DEC_D : std_logic_vector( 7 downto 0); -- D - 1
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signal L_DOUT : std_logic_vector(15 downto 0);
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signal L_DOUT : std_logic_vector(15 downto 0);
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signal L_INC_D : std_logic_vector( 7 downto 0); -- D + 1
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signal L_INC_D : std_logic_vector( 7 downto 0); -- D + 1
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signal L_LSR_D : std_logic_vector( 7 downto 0); -- (unsigned) D >> 1
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signal L_LSR_D : std_logic_vector( 7 downto 0); -- (unsigned) D >> 1
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signal L_MASK_I : std_logic_vector( 7 downto 0); -- 1 << IMM
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signal L_MASK_I : std_logic_vector( 7 downto 0); -- 1 << IMM
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signal L_NEG_D : std_logic_vector( 7 downto 0); -- 0 - D
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signal L_NEG_D : std_logic_vector( 7 downto 0); -- 0 - D
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signal L_NOT_D : std_logic_vector( 7 downto 0); -- 0 not D
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signal L_NOT_D : std_logic_vector( 7 downto 0); -- 0 not D
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signal L_OR_DR : std_logic_vector( 7 downto 0); -- D or R
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signal L_OR_DR : std_logic_vector( 7 downto 0); -- D or R
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signal L_PROD : std_logic_vector(17 downto 0); -- D * R
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signal L_PROD : std_logic_vector(17 downto 0); -- D * R
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signal L_R8 : std_logic_vector( 7 downto 0); -- odd or even R
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signal L_R8 : std_logic_vector( 7 downto 0); -- odd or even R
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signal L_RI8 : std_logic_vector( 7 downto 0); -- R8 or IMM
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signal L_RI8 : std_logic_vector( 7 downto 0); -- R8 or IMM
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signal L_RBIT : std_logic;
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signal L_RBIT : std_logic;
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signal L_SBIW_D : std_logic_vector(15 downto 0); -- D - IMM
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signal L_SBIW_D : std_logic_vector(15 downto 0); -- D - IMM
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signal L_ROR_D : std_logic_vector( 7 downto 0); -- D rotated right
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signal L_ROR_D : std_logic_vector( 7 downto 0); -- D rotated right
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signal L_SBC_DR : std_logic_vector( 7 downto 0); -- D - R - Carry
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signal L_SBC_DR : std_logic_vector( 7 downto 0); -- D - R - Carry
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signal L_SIGN_D : std_logic;
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signal L_SIGN_D : std_logic;
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signal L_SIGN_R : std_logic;
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signal L_SIGN_R : std_logic;
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signal L_SUB_DR : std_logic_vector( 7 downto 0); -- D - R
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signal L_SUB_DR : std_logic_vector( 7 downto 0); -- D - R
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signal L_SWAP_D : std_logic_vector( 7 downto 0); -- D swapped
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signal L_SWAP_D : std_logic_vector( 7 downto 0); -- D swapped
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signal L_XOR_DR : std_logic_vector( 7 downto 0); -- D xor R
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signal L_XOR_DR : std_logic_vector( 7 downto 0); -- D xor R
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begin
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begin
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dinbit: process(I_DIN, I_BIT(2 downto 0))
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dinbit: process(I_DIN, I_BIT(2 downto 0))
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begin
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begin
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case I_BIT(2 downto 0) is
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case I_BIT(2 downto 0) is
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when "000" => L_RBIT <= I_DIN(0); L_MASK_I <= "00000001";
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when "000" => L_RBIT <= I_DIN(0); L_MASK_I <= "00000001";
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when "001" => L_RBIT <= I_DIN(1); L_MASK_I <= "00000010";
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when "001" => L_RBIT <= I_DIN(1); L_MASK_I <= "00000010";
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when "010" => L_RBIT <= I_DIN(2); L_MASK_I <= "00000100";
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when "010" => L_RBIT <= I_DIN(2); L_MASK_I <= "00000100";
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when "011" => L_RBIT <= I_DIN(3); L_MASK_I <= "00001000";
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when "011" => L_RBIT <= I_DIN(3); L_MASK_I <= "00001000";
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when "100" => L_RBIT <= I_DIN(4); L_MASK_I <= "00010000";
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when "100" => L_RBIT <= I_DIN(4); L_MASK_I <= "00010000";
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when "101" => L_RBIT <= I_DIN(5); L_MASK_I <= "00100000";
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when "101" => L_RBIT <= I_DIN(5); L_MASK_I <= "00100000";
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when "110" => L_RBIT <= I_DIN(6); L_MASK_I <= "01000000";
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when "110" => L_RBIT <= I_DIN(6); L_MASK_I <= "01000000";
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when others => L_RBIT <= I_DIN(7); L_MASK_I <= "10000000";
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when others => L_RBIT <= I_DIN(7); L_MASK_I <= "10000000";
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end case;
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end case;
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end process;
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end process;
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process(L_ADC_DR, L_ADD_DR, L_ADIW_D, I_ALU_OP, L_AND_DR, L_ASR_D,
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process(L_ADC_DR, L_ADD_DR, L_ADIW_D, I_ALU_OP, L_AND_DR, L_ASR_D,
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I_BIT, I_D, L_D8, L_DEC_D, I_DIN, I_FLAGS, I_IMM, L_MASK_I,
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I_BIT, I_D, L_D8, L_DEC_D, I_DIN, I_FLAGS, I_IMM, L_MASK_I,
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L_INC_D, L_LSR_D, L_NEG_D, L_NOT_D, L_OR_DR, I_PC, L_PROD,
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L_INC_D, L_LSR_D, L_NEG_D, L_NOT_D, L_OR_DR, I_PC, L_PROD,
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I_R, L_RI8, L_RBIT, L_ROR_D, L_SBIW_D, L_SUB_DR, L_SBC_DR,
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I_R, L_RI8, L_RBIT, L_ROR_D, L_SBIW_D, L_SUB_DR, L_SBC_DR,
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L_SIGN_D, L_SIGN_R, L_SWAP_D, L_XOR_DR)
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L_SIGN_D, L_SIGN_R, L_SWAP_D, L_XOR_DR)
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begin
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begin
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Q_FLAGS(9) <= L_RBIT xor not I_BIT(3); -- DIN[BIT] = BIT[3]
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Q_FLAGS(9) <= L_RBIT xor not I_BIT(3); -- DIN[BIT] = BIT[3]
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Q_FLAGS(8) <= ze(L_SUB_DR); -- D == R for CPSE
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Q_FLAGS(8) <= ze(L_SUB_DR); -- D == R for CPSE
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Q_FLAGS(7 downto 0) <= I_FLAGS;
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Q_FLAGS(7 downto 0) <= I_FLAGS;
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L_DOUT <= X"0000";
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L_DOUT <= X"0000";
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case I_ALU_OP is
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case I_ALU_OP is
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when ALU_ADC =>
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when ALU_ADC =>
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L_DOUT <= L_ADC_DR & L_ADC_DR;
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L_DOUT <= L_ADC_DR & L_ADC_DR;
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Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Carry
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Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Carry
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Q_FLAGS(1) <= ze(L_ADC_DR); -- Zero
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Q_FLAGS(1) <= ze(L_ADC_DR); -- Zero
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Q_FLAGS(2) <= L_ADC_DR(7); -- Negative
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Q_FLAGS(2) <= L_ADC_DR(7); -- Negative
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Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Overflow
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Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Overflow
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Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Signed
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Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Signed
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Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADC_DR(3)); -- Halfcarry
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Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADC_DR(3)); -- Halfcarry
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when ALU_ADD =>
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when ALU_ADD =>
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L_DOUT <= L_ADD_DR & L_ADD_DR;
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L_DOUT <= L_ADD_DR & L_ADD_DR;
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Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Carry
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Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Carry
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Q_FLAGS(1) <= ze(L_ADD_DR); -- Zero
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Q_FLAGS(1) <= ze(L_ADD_DR); -- Zero
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Q_FLAGS(2) <= L_ADD_DR(7); -- Negative
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Q_FLAGS(2) <= L_ADD_DR(7); -- Negative
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Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Overflow
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Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Overflow
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Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Signed
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Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Signed
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Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADD_DR(3)); -- Halfcarry
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Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADD_DR(3)); -- Halfcarry
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when ALU_ADIW =>
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when ALU_ADIW =>
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L_DOUT <= L_ADIW_D;
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L_DOUT <= L_ADIW_D;
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Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15); -- Carry
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Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15); -- Carry
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Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
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Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
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ze(L_ADIW_D(7 downto 0)); -- Zero
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ze(L_ADIW_D(7 downto 0)); -- Zero
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Q_FLAGS(2) <= L_ADIW_D(15); -- Negative
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Q_FLAGS(2) <= L_ADIW_D(15); -- Negative
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Q_FLAGS(3) <= I_D(15) and not L_ADIW_D(15); -- Overflow
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Q_FLAGS(3) <= I_D(15) and not L_ADIW_D(15); -- Overflow
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Q_FLAGS(4) <= (L_ADIW_D(15) and not I_D(15))
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Q_FLAGS(4) <= (L_ADIW_D(15) and not I_D(15))
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xor (I_D(15) and not L_ADIW_D(15)); -- Signed
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xor (I_D(15) and not L_ADIW_D(15)); -- Signed
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when ALU_AND =>
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when ALU_AND =>
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L_DOUT <= L_AND_DR & L_AND_DR;
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L_DOUT <= L_AND_DR & L_AND_DR;
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Q_FLAGS(1) <= ze(L_AND_DR); -- Zero
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Q_FLAGS(1) <= ze(L_AND_DR); -- Zero
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Q_FLAGS(2) <= L_AND_DR(7); -- Negative
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Q_FLAGS(2) <= L_AND_DR(7); -- Negative
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Q_FLAGS(3) <= '0'; -- Overflow
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Q_FLAGS(3) <= '0'; -- Overflow
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Q_FLAGS(4) <= L_AND_DR(7); -- Signed
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Q_FLAGS(4) <= L_AND_DR(7); -- Signed
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when ALU_ASR =>
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when ALU_ASR =>
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L_DOUT <= L_ASR_D & L_ASR_D;
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L_DOUT <= L_ASR_D & L_ASR_D;
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Q_FLAGS(0) <= L_D8(0); -- Carry
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Q_FLAGS(0) <= L_D8(0); -- Carry
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Q_FLAGS(1) <= ze(L_ASR_D); -- Zero
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Q_FLAGS(1) <= ze(L_ASR_D); -- Zero
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Q_FLAGS(2) <= L_D8(7); -- Negative
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Q_FLAGS(2) <= L_D8(7); -- Negative
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Q_FLAGS(3) <= L_D8(0) xor L_D8(7); -- Overflow
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Q_FLAGS(3) <= L_D8(0) xor L_D8(7); -- Overflow
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Q_FLAGS(4) <= L_D8(0); -- Signed
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Q_FLAGS(4) <= L_D8(0); -- Signed
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|
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when ALU_BLD => -- copy T flag to DOUT
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when ALU_BLD => -- copy T flag to DOUT
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case I_BIT(2 downto 0) is
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case I_BIT(2 downto 0) is
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when "000" => L_DOUT( 0) <= I_FLAGS(6);
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when "000" => L_DOUT( 0) <= I_FLAGS(6);
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L_DOUT( 8) <= I_FLAGS(6);
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L_DOUT( 8) <= I_FLAGS(6);
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when "001" => L_DOUT( 1) <= I_FLAGS(6);
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when "001" => L_DOUT( 1) <= I_FLAGS(6);
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L_DOUT( 9) <= I_FLAGS(6);
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L_DOUT( 9) <= I_FLAGS(6);
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when "010" => L_DOUT( 2) <= I_FLAGS(6);
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when "010" => L_DOUT( 2) <= I_FLAGS(6);
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L_DOUT(10) <= I_FLAGS(6);
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L_DOUT(10) <= I_FLAGS(6);
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when "011" => L_DOUT( 3) <= I_FLAGS(6);
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when "011" => L_DOUT( 3) <= I_FLAGS(6);
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L_DOUT(11) <= I_FLAGS(6);
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L_DOUT(11) <= I_FLAGS(6);
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when "100" => L_DOUT( 4) <= I_FLAGS(6);
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when "100" => L_DOUT( 4) <= I_FLAGS(6);
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L_DOUT(12) <= I_FLAGS(6);
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L_DOUT(12) <= I_FLAGS(6);
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when "101" => L_DOUT( 5) <= I_FLAGS(6);
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when "101" => L_DOUT( 5) <= I_FLAGS(6);
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L_DOUT(13) <= I_FLAGS(6);
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L_DOUT(13) <= I_FLAGS(6);
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when "110" => L_DOUT( 6) <= I_FLAGS(6);
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when "110" => L_DOUT( 6) <= I_FLAGS(6);
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L_DOUT(14) <= I_FLAGS(6);
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L_DOUT(14) <= I_FLAGS(6);
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when others => L_DOUT( 7) <= I_FLAGS(6);
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when others => L_DOUT( 7) <= I_FLAGS(6);
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L_DOUT(15) <= I_FLAGS(6);
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L_DOUT(15) <= I_FLAGS(6);
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end case;
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end case;
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|
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when ALU_BIT_CS => -- copy I_DIN to T flag
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when ALU_BIT_CS => -- copy I_DIN to T flag
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Q_FLAGS(6) <= L_RBIT xor not I_BIT(3);
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Q_FLAGS(6) <= L_RBIT xor not I_BIT(3);
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if (I_BIT(3) = '0') then -- clear
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if (I_BIT(3) = '0') then -- clear
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L_DOUT(15 downto 8) <= I_DIN and not L_MASK_I;
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L_DOUT(15 downto 8) <= I_DIN and not L_MASK_I;
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L_DOUT( 7 downto 0) <= I_DIN and not L_MASK_I;
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L_DOUT( 7 downto 0) <= I_DIN and not L_MASK_I;
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else -- set
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else -- set
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L_DOUT(15 downto 8) <= I_DIN or L_MASK_I;
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L_DOUT(15 downto 8) <= I_DIN or L_MASK_I;
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L_DOUT( 7 downto 0) <= I_DIN or L_MASK_I;
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L_DOUT( 7 downto 0) <= I_DIN or L_MASK_I;
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end if;
|
end if;
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|
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when ALU_COM =>
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when ALU_COM =>
|
L_DOUT <= L_NOT_D & L_NOT_D;
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L_DOUT <= L_NOT_D & L_NOT_D;
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Q_FLAGS(0) <= '1'; -- Carry
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Q_FLAGS(0) <= '1'; -- Carry
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Q_FLAGS(1) <= ze(not L_D8); -- Zero
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Q_FLAGS(1) <= ze(not L_D8); -- Zero
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Q_FLAGS(2) <= not L_D8(7); -- Negative
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Q_FLAGS(2) <= not L_D8(7); -- Negative
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Q_FLAGS(3) <= '0'; -- Overflow
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Q_FLAGS(3) <= '0'; -- Overflow
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Q_FLAGS(4) <= not L_D8(7); -- Signed
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Q_FLAGS(4) <= not L_D8(7); -- Signed
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|
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when ALU_DEC =>
|
when ALU_DEC =>
|
L_DOUT <= L_DEC_D & L_DEC_D;
|
L_DOUT <= L_DEC_D & L_DEC_D;
|
Q_FLAGS(1) <= ze(L_DEC_D); -- Zero
|
Q_FLAGS(1) <= ze(L_DEC_D); -- Zero
|
Q_FLAGS(2) <= L_DEC_D(7); -- Negative
|
Q_FLAGS(2) <= L_DEC_D(7); -- Negative
|
if (L_D8 = X"80") then
|
if (L_D8 = X"80") then
|
Q_FLAGS(3) <= '1'; -- Overflow
|
Q_FLAGS(3) <= '1'; -- Overflow
|
Q_FLAGS(4) <= not L_DEC_D(7); -- Signed
|
Q_FLAGS(4) <= not L_DEC_D(7); -- Signed
|
else
|
else
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(4) <= L_DEC_D(7); -- Signed
|
Q_FLAGS(4) <= L_DEC_D(7); -- Signed
|
end if;
|
end if;
|
|
|
when ALU_EOR =>
|
when ALU_EOR =>
|
L_DOUT <= L_XOR_DR & L_XOR_DR;
|
L_DOUT <= L_XOR_DR & L_XOR_DR;
|
Q_FLAGS(1) <= ze(L_XOR_DR); -- Zero
|
Q_FLAGS(1) <= ze(L_XOR_DR); -- Zero
|
Q_FLAGS(2) <= L_XOR_DR(7); -- Negative
|
Q_FLAGS(2) <= L_XOR_DR(7); -- Negative
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(4) <= L_XOR_DR(7); -- Signed
|
Q_FLAGS(4) <= L_XOR_DR(7); -- Signed
|
|
|
when ALU_INC =>
|
when ALU_INC =>
|
L_DOUT <= L_INC_D & L_INC_D;
|
L_DOUT <= L_INC_D & L_INC_D;
|
Q_FLAGS(1) <= ze(L_INC_D); -- Zero
|
Q_FLAGS(1) <= ze(L_INC_D); -- Zero
|
Q_FLAGS(2) <= L_INC_D(7); -- Negative
|
Q_FLAGS(2) <= L_INC_D(7); -- Negative
|
if (L_D8 = X"7F") then
|
if (L_D8 = X"7F") then
|
Q_FLAGS(3) <= '1'; -- Overflow
|
Q_FLAGS(3) <= '1'; -- Overflow
|
Q_FLAGS(4) <= not L_INC_D(7); -- Signed
|
Q_FLAGS(4) <= not L_INC_D(7); -- Signed
|
else
|
else
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(4) <= L_INC_D(7); -- Signed
|
Q_FLAGS(4) <= L_INC_D(7); -- Signed
|
end if;
|
end if;
|
|
|
when ALU_INTR =>
|
when ALU_INTR =>
|
L_DOUT <= I_PC;
|
L_DOUT <= I_PC;
|
Q_FLAGS(7) <= I_IMM(6); -- ena/disable interrupts
|
Q_FLAGS(7) <= I_IMM(6); -- ena/disable interrupts
|
|
|
when ALU_LSR =>
|
when ALU_LSR =>
|
L_DOUT <= L_LSR_D & L_LSR_D;
|
L_DOUT <= L_LSR_D & L_LSR_D;
|
Q_FLAGS(0) <= L_D8(0); -- Carry
|
Q_FLAGS(0) <= L_D8(0); -- Carry
|
Q_FLAGS(1) <= ze(L_LSR_D); -- Zero
|
Q_FLAGS(1) <= ze(L_LSR_D); -- Zero
|
Q_FLAGS(2) <= '0'; -- Negative
|
Q_FLAGS(2) <= '0'; -- Negative
|
Q_FLAGS(3) <= L_D8(0); -- Overflow
|
Q_FLAGS(3) <= L_D8(0); -- Overflow
|
Q_FLAGS(4) <= L_D8(0); -- Signed
|
Q_FLAGS(4) <= L_D8(0); -- Signed
|
|
|
when ALU_D_MV_Q =>
|
when ALU_D_MV_Q =>
|
L_DOUT <= L_D8 & L_D8;
|
L_DOUT <= L_D8 & L_D8;
|
|
|
when ALU_R_MV_Q =>
|
when ALU_R_MV_Q =>
|
L_DOUT <= L_RI8 & L_RI8;
|
L_DOUT <= L_RI8 & L_RI8;
|
|
|
when ALU_MV_16 =>
|
when ALU_MV_16 =>
|
L_DOUT <= I_R(15 downto 8) & L_RI8;
|
L_DOUT <= I_R(15 downto 8) & L_RI8;
|
|
|
when ALU_MULT =>
|
when ALU_MULT =>
|
Q_FLAGS(0) <= L_PROD(15); -- Carry
|
Q_FLAGS(0) <= L_PROD(15); -- Carry
|
if I_IMM(7) = '0' then -- MUL
|
if I_IMM(7) = '0' then -- MUL
|
L_DOUT <= L_PROD(15 downto 0);
|
L_DOUT <= L_PROD(15 downto 0);
|
Q_FLAGS(1) <= ze(L_PROD(15 downto 8)) -- Zero
|
Q_FLAGS(1) <= ze(L_PROD(15 downto 8)) -- Zero
|
and ze(L_PROD( 7 downto 0));
|
and ze(L_PROD( 7 downto 0));
|
else -- FMUL
|
else -- FMUL
|
L_DOUT <= L_PROD(14 downto 0) & "0";
|
L_DOUT <= L_PROD(14 downto 0) & "0";
|
Q_FLAGS(1) <= ze(L_PROD(14 downto 7)) -- Zero
|
Q_FLAGS(1) <= ze(L_PROD(14 downto 7)) -- Zero
|
and ze(L_PROD( 6 downto 0) & "0");
|
and ze(L_PROD( 6 downto 0) & "0");
|
end if;
|
end if;
|
|
|
when ALU_NEG =>
|
when ALU_NEG =>
|
L_DOUT <= L_NEG_D & L_NEG_D;
|
L_DOUT <= L_NEG_D & L_NEG_D;
|
Q_FLAGS(0) <= not ze(L_D8); -- Carry
|
Q_FLAGS(0) <= not ze(L_D8); -- Carry
|
Q_FLAGS(1) <= ze(L_NEG_D); -- Zero
|
Q_FLAGS(1) <= ze(L_NEG_D); -- Zero
|
Q_FLAGS(2) <= L_NEG_D(7); -- Negative
|
Q_FLAGS(2) <= L_NEG_D(7); -- Negative
|
if (L_D8 = X"80") then
|
if (L_D8 = X"80") then
|
Q_FLAGS(3) <= '1'; -- Overflow
|
Q_FLAGS(3) <= '1'; -- Overflow
|
Q_FLAGS(4) <= not L_NEG_D(7); -- Signed
|
Q_FLAGS(4) <= not L_NEG_D(7); -- Signed
|
else
|
else
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(4) <= L_NEG_D(7); -- Signed
|
Q_FLAGS(4) <= L_NEG_D(7); -- Signed
|
end if;
|
end if;
|
Q_FLAGS(5) <= L_D8(3) or L_NEG_D(3); -- Halfcarry
|
Q_FLAGS(5) <= L_D8(3) or L_NEG_D(3); -- Halfcarry
|
|
|
when ALU_OR =>
|
when ALU_OR =>
|
L_DOUT <= L_OR_DR & L_OR_DR;
|
L_DOUT <= L_OR_DR & L_OR_DR;
|
Q_FLAGS(1) <= ze(L_OR_DR); -- Zero
|
Q_FLAGS(1) <= ze(L_OR_DR); -- Zero
|
Q_FLAGS(2) <= L_OR_DR(7); -- Negative
|
Q_FLAGS(2) <= L_OR_DR(7); -- Negative
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(3) <= '0'; -- Overflow
|
Q_FLAGS(4) <= L_OR_DR(7); -- Signed
|
Q_FLAGS(4) <= L_OR_DR(7); -- Signed
|
|
|
when ALU_PC_1 => -- ICALL, RCALL
|
when ALU_PC_1 => -- ICALL, RCALL
|
L_DOUT <= I_PC + X"0001";
|
L_DOUT <= I_PC + X"0001";
|
|
|
when ALU_PC_2 => -- CALL
|
when ALU_PC_2 => -- CALL
|
L_DOUT <= I_PC + X"0002";
|
L_DOUT <= I_PC + X"0002";
|
|
|
when ALU_ROR =>
|
when ALU_ROR =>
|
L_DOUT <= L_ROR_D & L_ROR_D;
|
L_DOUT <= L_ROR_D & L_ROR_D;
|
|
Q_FLAGS(0) <= L_D8(0); -- Carry
|
Q_FLAGS(1) <= ze(L_ROR_D); -- Zero
|
Q_FLAGS(1) <= ze(L_ROR_D); -- Zero
|
Q_FLAGS(2) <= I_FLAGS(0); -- Negative
|
Q_FLAGS(2) <= I_FLAGS(0); -- Negative
|
Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0); -- Overflow
|
Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0); -- Overflow
|
Q_FLAGS(4) <= I_FLAGS(0); -- Signed
|
Q_FLAGS(4) <= I_FLAGS(0); -- Signed
|
|
|
when ALU_SBC =>
|
when ALU_SBC =>
|
L_DOUT <= L_SBC_DR & L_SBC_DR;
|
L_DOUT <= L_SBC_DR & L_SBC_DR;
|
Q_FLAGS(0) <= cy(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Carry
|
Q_FLAGS(0) <= cy(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Carry
|
Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1); -- Zero
|
Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1); -- Zero
|
Q_FLAGS(2) <= L_SBC_DR(7); -- Negative
|
Q_FLAGS(2) <= L_SBC_DR(7); -- Negative
|
Q_FLAGS(3) <= ov(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Overflow
|
Q_FLAGS(3) <= ov(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Overflow
|
Q_FLAGS(4) <= si(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Signed
|
Q_FLAGS(4) <= si(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Signed
|
Q_FLAGS(5) <= cy(L_SBC_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
|
Q_FLAGS(5) <= cy(L_SBC_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
|
|
|
when ALU_SBIW =>
|
when ALU_SBIW =>
|
L_DOUT <= L_SBIW_D;
|
L_DOUT <= L_SBIW_D;
|
Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15); -- Carry
|
Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15); -- Carry
|
Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
|
Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
|
ze(L_SBIW_D(7 downto 0)); -- Zero
|
ze(L_SBIW_D(7 downto 0)); -- Zero
|
Q_FLAGS(2) <= L_SBIW_D(15); -- Negative
|
Q_FLAGS(2) <= L_SBIW_D(15); -- Negative
|
Q_FLAGS(3) <= I_D(15) and not L_SBIW_D(15); -- Overflow
|
Q_FLAGS(3) <= I_D(15) and not L_SBIW_D(15); -- Overflow
|
Q_FLAGS(4) <= (L_SBIW_D(15) and not I_D(15))
|
Q_FLAGS(4) <= (L_SBIW_D(15) and not I_D(15))
|
xor (I_D(15) and not L_SBIW_D(15)); -- Signed
|
xor (I_D(15) and not L_SBIW_D(15)); -- Signed
|
|
|
when ALU_SREG =>
|
when ALU_SREG =>
|
case I_BIT(2 downto 0) is
|
case I_BIT(2 downto 0) is
|
when "000" => Q_FLAGS(0) <= not I_BIT(3);
|
when "000" => Q_FLAGS(0) <= not I_BIT(3);
|
when "001" => Q_FLAGS(1) <= not I_BIT(3);
|
when "001" => Q_FLAGS(1) <= not I_BIT(3);
|
when "010" => Q_FLAGS(2) <= not I_BIT(3);
|
when "010" => Q_FLAGS(2) <= not I_BIT(3);
|
when "011" => Q_FLAGS(3) <= not I_BIT(3);
|
when "011" => Q_FLAGS(3) <= not I_BIT(3);
|
when "100" => Q_FLAGS(4) <= not I_BIT(3);
|
when "100" => Q_FLAGS(4) <= not I_BIT(3);
|
when "101" => Q_FLAGS(5) <= not I_BIT(3);
|
when "101" => Q_FLAGS(5) <= not I_BIT(3);
|
when "110" => Q_FLAGS(6) <= not I_BIT(3);
|
when "110" => Q_FLAGS(6) <= not I_BIT(3);
|
when others => Q_FLAGS(7) <= not I_BIT(3);
|
when others => Q_FLAGS(7) <= not I_BIT(3);
|
end case;
|
end case;
|
|
|
when ALU_SUB =>
|
when ALU_SUB =>
|
L_DOUT <= L_SUB_DR & L_SUB_DR;
|
L_DOUT <= L_SUB_DR & L_SUB_DR;
|
Q_FLAGS(0) <= cy(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Carry
|
Q_FLAGS(0) <= cy(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Carry
|
Q_FLAGS(1) <= ze(L_SUB_DR); -- Zero
|
Q_FLAGS(1) <= ze(L_SUB_DR); -- Zero
|
Q_FLAGS(2) <= L_SUB_DR(7); -- Negative
|
Q_FLAGS(2) <= L_SUB_DR(7); -- Negative
|
Q_FLAGS(3) <= ov(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Overflow
|
Q_FLAGS(3) <= ov(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Overflow
|
Q_FLAGS(4) <= si(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Signed
|
Q_FLAGS(4) <= si(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Signed
|
Q_FLAGS(5) <= cy(L_SUB_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
|
Q_FLAGS(5) <= cy(L_SUB_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
|
|
|
when ALU_SWAP =>
|
when ALU_SWAP =>
|
L_DOUT <= L_SWAP_D & L_SWAP_D;
|
L_DOUT <= L_SWAP_D & L_SWAP_D;
|
|
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
L_D8 <= I_D(15 downto 8) when (I_D0 = '1') else I_D(7 downto 0);
|
L_D8 <= I_D(15 downto 8) when (I_D0 = '1') else I_D(7 downto 0);
|
L_R8 <= I_R(15 downto 8) when (I_R0 = '1') else I_R(7 downto 0);
|
L_R8 <= I_R(15 downto 8) when (I_R0 = '1') else I_R(7 downto 0);
|
L_RI8 <= I_IMM when (I_RSEL = RS_IMM) else L_R8;
|
L_RI8 <= I_IMM when (I_RSEL = RS_IMM) else L_R8;
|
|
|
L_ADIW_D <= I_D + ("0000000000" & I_IMM(5 downto 0));
|
L_ADIW_D <= I_D + ("0000000000" & I_IMM(5 downto 0));
|
L_SBIW_D <= I_D - ("0000000000" & I_IMM(5 downto 0));
|
L_SBIW_D <= I_D - ("0000000000" & I_IMM(5 downto 0));
|
L_ADD_DR <= L_D8 + L_RI8;
|
L_ADD_DR <= L_D8 + L_RI8;
|
L_ADC_DR <= L_ADD_DR + ("0000000" & I_FLAGS(0));
|
L_ADC_DR <= L_ADD_DR + ("0000000" & I_FLAGS(0));
|
L_ASR_D <= L_D8(7) & L_D8(7 downto 1);
|
L_ASR_D <= L_D8(7) & L_D8(7 downto 1);
|
L_AND_DR <= L_D8 and L_RI8;
|
L_AND_DR <= L_D8 and L_RI8;
|
L_DEC_D <= L_D8 - X"01";
|
L_DEC_D <= L_D8 - X"01";
|
L_INC_D <= L_D8 + X"01";
|
L_INC_D <= L_D8 + X"01";
|
L_LSR_D <= '0' & L_D8(7 downto 1);
|
L_LSR_D <= '0' & L_D8(7 downto 1);
|
L_NEG_D <= X"00" - L_D8;
|
L_NEG_D <= X"00" - L_D8;
|
L_NOT_D <= not L_D8;
|
L_NOT_D <= not L_D8;
|
L_OR_DR <= L_D8 or L_RI8;
|
L_OR_DR <= L_D8 or L_RI8;
|
L_PROD <= (L_SIGN_D & L_D8) * (L_SIGN_R & L_R8);
|
L_PROD <= (L_SIGN_D & L_D8) * (L_SIGN_R & L_R8);
|
L_ROR_D <= I_FLAGS(0) & L_D8(7 downto 1);
|
L_ROR_D <= I_FLAGS(0) & L_D8(7 downto 1);
|
L_SUB_DR <= L_D8 - L_RI8;
|
L_SUB_DR <= L_D8 - L_RI8;
|
L_SBC_DR <= L_SUB_DR - ("0000000" & I_FLAGS(0));
|
L_SBC_DR <= L_SUB_DR - ("0000000" & I_FLAGS(0));
|
L_SIGN_D <= L_D8(7) and I_IMM(6);
|
L_SIGN_D <= L_D8(7) and I_IMM(6);
|
L_SIGN_R <= L_R8(7) and I_IMM(5);
|
L_SIGN_R <= L_R8(7) and I_IMM(5);
|
L_SWAP_D <= L_D8(3 downto 0) & L_D8(7 downto 4);
|
L_SWAP_D <= L_D8(3 downto 0) & L_D8(7 downto 4);
|
L_XOR_DR <= L_D8 xor L_R8;
|
L_XOR_DR <= L_D8 xor L_R8;
|
|
|
Q_DOUT <= (I_DIN & I_DIN) when (I_RSEL = RS_DIN) else L_DOUT;
|
Q_DOUT <= (I_DIN & I_DIN) when (I_RSEL = RS_DIN) else L_DOUT;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
