| Line 55... |
Line 55... |
begin
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begin
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return not (A(0) or A(1) or A(2) or A(3) or
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return not (A(0) or A(1) or A(2) or A(3) or
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A(4) or A(5) or A(6) or A(7));
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A(4) or A(5) or A(6) or A(7));
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end;
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end;
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function cy(D, R, S: std_logic) return std_logic is
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function cy_add(Rd, Rr, R: std_logic) return std_logic is
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begin
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begin
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return (D and R) or (D and not S) or (R and not S);
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return (Rd and Rr) or (Rd and (not R)) or ((not R) and Rr);
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end;
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end;
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function ov(D, R, S: std_logic) return std_logic is
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function ov_add(Rd, Rr, R: std_logic) return std_logic is
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begin
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begin
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return (D and R and (not S)) or ((not D) and (not R) and S);
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return (Rd and Rr and (not R)) or ((not Rd) and (not Rr) and R);
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end;
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end;
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function si(D, R, S: std_logic) return std_logic is
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function si_add(Rd, Rr, R: std_logic) return std_logic is
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begin
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begin
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return S xor ov(D, R, S);
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return R xor ov_add(Rd, Rr, R);
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end;
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function cy_sub(Rd, Rr, R: std_logic) return std_logic is
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begin
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return ((not Rd) and Rr) or (Rr and R) or (R and (not Rd));
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end;
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function ov_sub(Rd, Rr, R: std_logic) return std_logic is
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begin
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return (Rd and (not Rr) and (not R)) or ((not Rd) and Rr and R);
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end;
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function si_sub(Rd, Rr, R: std_logic) return std_logic is
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begin
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return R xor ov_sub(Rd, Rr, R);
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end;
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end;
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signal L_ADC_DR : std_logic_vector( 7 downto 0); -- D + R + Carry
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signal L_ADC_DR : std_logic_vector( 7 downto 0); -- D + R + Carry
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signal L_ADD_DR : std_logic_vector( 7 downto 0); -- D + R
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signal L_ADD_DR : std_logic_vector( 7 downto 0); -- D + R
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signal L_ADIW_D : std_logic_vector(15 downto 0); -- D + IMM
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signal L_ADIW_D : std_logic_vector(15 downto 0); -- D + IMM
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| Line 127... |
Line 142... |
L_DOUT <= X"0000";
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L_DOUT <= X"0000";
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|
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case I_ALU_OP is
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case I_ALU_OP is
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when ALU_ADC =>
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when ALU_ADC =>
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L_DOUT <= L_ADC_DR & L_ADC_DR;
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L_DOUT <= L_ADC_DR & L_ADC_DR;
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Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Carry
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Q_FLAGS(0) <= cy_add(L_D8(7), L_RI8(7), L_ADC_DR(7));-- Carry
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Q_FLAGS(1) <= ze(L_ADC_DR); -- Zero
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Q_FLAGS(1) <= ze(L_ADC_DR); -- Zero
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Q_FLAGS(2) <= L_ADC_DR(7); -- Negative
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Q_FLAGS(2) <= L_ADC_DR(7); -- Negative
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Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Overflow
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Q_FLAGS(3) <= ov_add(L_D8(7), L_RI8(7), L_ADC_DR(7));-- Overflow
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Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Signed
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Q_FLAGS(4) <= si_add(L_D8(7), L_RI8(7), L_ADC_DR(7));-- Signed
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Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADC_DR(3)); -- Halfcarry
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Q_FLAGS(5) <= cy_add(L_D8(3), L_RI8(3), L_ADC_DR(3));-- Halfcarry
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when ALU_ADD =>
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when ALU_ADD =>
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L_DOUT <= L_ADD_DR & L_ADD_DR;
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L_DOUT <= L_ADD_DR & L_ADD_DR;
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Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Carry
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Q_FLAGS(0) <= cy_add(L_D8(7), L_RI8(7), L_ADD_DR(7));-- Carry
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Q_FLAGS(1) <= ze(L_ADD_DR); -- Zero
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Q_FLAGS(1) <= ze(L_ADD_DR); -- Zero
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Q_FLAGS(2) <= L_ADD_DR(7); -- Negative
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Q_FLAGS(2) <= L_ADD_DR(7); -- Negative
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Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Overflow
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Q_FLAGS(3) <= ov_add(L_D8(7), L_RI8(7), L_ADD_DR(7));-- Overflow
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Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Signed
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Q_FLAGS(4) <= si_add(L_D8(7), L_RI8(7), L_ADD_DR(7));-- Signed
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Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADD_DR(3)); -- Halfcarry
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Q_FLAGS(5) <= cy_add(L_D8(3), L_RI8(3), L_ADD_DR(3));-- Halfcarry
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|
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when ALU_ADIW =>
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when ALU_ADIW =>
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L_DOUT <= L_ADIW_D;
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L_DOUT <= L_ADIW_D;
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Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15); -- Carry
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Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15); -- Carry
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Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
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Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
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| Line 307... |
Line 322... |
Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0); -- Overflow
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Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0); -- Overflow
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Q_FLAGS(4) <= I_FLAGS(0); -- Signed
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Q_FLAGS(4) <= I_FLAGS(0); -- Signed
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|
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when ALU_SBC =>
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when ALU_SBC =>
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L_DOUT <= L_SBC_DR & L_SBC_DR;
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L_DOUT <= L_SBC_DR & L_SBC_DR;
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Q_FLAGS(0) <= cy(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Carry
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Q_FLAGS(0) <= cy_sub(L_D8(7), L_RI8(7), L_SBC_DR(7));-- Carry
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Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1); -- Zero
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Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1); -- Zero
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Q_FLAGS(2) <= L_SBC_DR(7); -- Negative
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Q_FLAGS(2) <= L_SBC_DR(7); -- Negative
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Q_FLAGS(3) <= ov(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Overflow
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Q_FLAGS(3) <= ov_sub(L_D8(7), L_RI8(7), L_SBC_DR(7));-- Overflow
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Q_FLAGS(4) <= si(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Signed
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Q_FLAGS(4) <= si_sub(L_D8(7), L_RI8(7), L_SBC_DR(7));-- Signed
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Q_FLAGS(5) <= cy(L_SBC_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
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Q_FLAGS(5) <= cy_sub(L_D8(3), L_RI8(3), L_SBC_DR(3));-- Halfcarry
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|
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when ALU_SBIW =>
|
when ALU_SBIW =>
|
L_DOUT <= L_SBIW_D;
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L_DOUT <= L_SBIW_D;
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Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15); -- Carry
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Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15); -- Carry
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Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
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Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
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| Line 338... |
Line 353... |
when others => Q_FLAGS(7) <= not I_BIT(3);
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when others => Q_FLAGS(7) <= not I_BIT(3);
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end case;
|
end case;
|
|
|
when ALU_SUB =>
|
when ALU_SUB =>
|
L_DOUT <= L_SUB_DR & L_SUB_DR;
|
L_DOUT <= L_SUB_DR & L_SUB_DR;
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Q_FLAGS(0) <= cy(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Carry
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Q_FLAGS(0) <= cy_sub(L_D8(7), L_RI8(7), L_SUB_DR(7));-- Carry
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Q_FLAGS(1) <= ze(L_SUB_DR); -- Zero
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Q_FLAGS(1) <= ze(L_SUB_DR); -- Zero
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Q_FLAGS(2) <= L_SUB_DR(7); -- Negative
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Q_FLAGS(2) <= L_SUB_DR(7); -- Negative
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Q_FLAGS(3) <= ov(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Overflow
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Q_FLAGS(3) <= ov_sub(L_D8(7), L_RI8(7), L_SUB_DR(7));-- Overflow
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Q_FLAGS(4) <= si(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Signed
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Q_FLAGS(4) <= si_sub(L_D8(7), L_RI8(7), L_SUB_DR(7));-- Signed
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Q_FLAGS(5) <= cy(L_SUB_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
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Q_FLAGS(5) <= cy_sub(L_D8(3), L_RI8(3), L_SUB_DR(3));-- Halfcarry
|
|
|
when ALU_SWAP =>
|
when ALU_SWAP =>
|
L_DOUT <= L_SWAP_D & L_SWAP_D;
|
L_DOUT <= L_SWAP_D & L_SWAP_D;
|
|
|
when others =>
|
when others =>
|
